2017-07-01 13:42:28 +08:00
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/*
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2018-10-22 11:02:14 +08:00
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* COPYRIGHT (C) 2018, Real-Thread Information Technology Ltd
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2021-04-09 10:52:34 +08:00
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*
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2018-10-22 11:02:14 +08:00
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* SPDX-License-Identifier: Apache-2.0
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2021-04-09 10:52:34 +08:00
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*
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2017-07-01 13:42:28 +08:00
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* Change Logs:
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* Date Author Notes
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* 2015-07-15 Bernard The first version
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*/
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#ifndef EMAC_DRV_H__
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#define EMAC_DRV_H__
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//#define ENHANCED_BD
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///* Ethernet standard lengths in bytes*/
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//#define ETH_ADDR_LEN (6)
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//#define ETH_TYPE_LEN (2)
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//#define ETH_CRC_LEN (4)
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//#define ETH_MAX_DATA (1500)
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//#define ETH_MIN_DATA (46)
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//#define ETH_HDR_LEN (ETH_ADDR_LEN * 2 + ETH_TYPE_LEN)
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//// 6 * 2 + 2 + 1500 + 4
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///* Maximum and Minimum Ethernet Frame Sizes */
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//#define ETH_MAX_FRM (ETH_HDR_LEN + ETH_MAX_DATA + ETH_CRC_LEN)
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//#define ETH_MIN_FRM (ETH_HDR_LEN + ETH_MIN_DATA + ETH_CRC_LEN)
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//#define ETH_MTU (ETH_HDR_LEN + ETH_MAX_DATA)
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///********INTERFACE**********/
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//typedef enum
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//{
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// MAC_MII,
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// MAC_RMII,
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//} ENET_INTERFACE;
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///********AUTONEG**********/
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//typedef enum
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//{
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// AUTONEG_ON,
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// AUTONEG_OFF
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//} ENET_AUTONEG;
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///********SPEED**********/
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//typedef enum
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//{
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// MII_10BASET,
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// MII_100BASET
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//} ENET_SPEED;
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///********DUPLEX**********/
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///* MII Duplex Settings */
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//typedef enum
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//{
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// MII_HDX, /*!< half-duplex */
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// MII_FDX /*!< full-duplex */
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//} ENET_DUPLEX;
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///********LOOPBACK**********/
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//typedef enum
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//{
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// INTERNAL_LOOPBACK,
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// EXTERNAL_LOOPBACK,
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// NO_LOOPBACK
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//} ENET_LOOPBACK;
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///********EXTERNAL**********/
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//typedef enum
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//{
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// EXTERNAL_NONE,
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// EXTERNAL_YES
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//} ENET_EXTERNAL_CONN;
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///*
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// * FEC Configuration Parameters
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// */
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//typedef struct
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//{
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// //ENET_Type* hw_base; /* FEC channel */
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// ENET_INTERFACE interface; /* Transceiver mode */
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// ENET_AUTONEG neg; /* FEC autoneg */
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// ENET_SPEED speed; /* Ethernet Speed */
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// ENET_DUPLEX duplex; /* Ethernet Duplex */
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// ENET_LOOPBACK loopback; /* Loopback Mode */
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// ENET_EXTERNAL_CONN external; /* outside test? */
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// uint8_t prom; /* Promiscuous Mode? */
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// uint8_t mac[6]; /* Ethernet Address */
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//} ENET_CONFIG;
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//// Choose Enhanced Buffer Descriptor or Legacy
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////#define ENHANCED_BD
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//// Buffer sizes in bytes (must be divisible by 16)
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//#define RX_BUFFER_SIZE ETH_MAX_FRM
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//#define TX_BUFFER_SIZE ETH_MAX_FRM
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//// Number of Receive and Transmit Buffers and Buffer Descriptors
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//#define NUM_RXBDS 8
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//#define NUM_TXBDS 4
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//// Buffer Descriptor Format
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//typedef struct
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//{
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// uint16_t status; /* control and status */
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// uint16_t length; /* transfer length */
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// uint8_t *data; /* buffer address */
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//#ifdef ENHANCED_BD
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// uint32_t ebd_status;
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// uint16_t length_proto_type;
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// uint16_t payload_checksum;
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// uint32_t bdu;
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// uint32_t timestamp;
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// uint32_t reserverd_word1;
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// uint32_t reserverd_word2;
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//#endif /* ENHANCED_BD */
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//} NBUF;
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//// ----------------------------------------------------------------------
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//// TX Buffer Descriptor Bit Definitions
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//// ----------------------------------------------------------------------
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//#define TX_BD_R 0x0080
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//#define TX_BD_TO1 0x0040
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//#define TX_BD_W 0x0020
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//#define TX_BD_TO2 0x0010
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//#define TX_BD_L 0x0008
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//#define TX_BD_TC 0x0004
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//#define TX_BD_ABC 0x0002
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//// ----------------------------------------------------------------------
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//// TX Enhanced BD Bit Definitions
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//// ----------------------------------------------------------------------
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//#define TX_BD_INT 0x00000040
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//#define TX_BD_TS 0x00000020
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//#define TX_BD_PINS 0x00000010
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//#define TX_BD_IINS 0x00000008
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//#define TX_BD_TXE 0x00800000
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//#define TX_BD_UE 0x00200000
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//#define TX_BD_EE 0x00100000
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//#define TX_BD_FE 0x00080000
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//#define TX_BD_LCE 0x00040000
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//#define TX_BD_OE 0x00020000
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//#define TX_BD_TSE 0x00010000
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//#define TX_BD_BDU 0x00000080
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//// ----------------------------------------------------------------------
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//// RX Buffer Descriptor Bit Definitions
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//// ----------------------------------------------------------------------
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//// Offset 0 flags - status: Big Endian
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//#define RX_BD_E 0x0080
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//#define RX_BD_R01 0x0040
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//#define RX_BD_W 0x0020
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//#define RX_BD_R02 0x0010
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//#define RX_BD_L 0x0008
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//#define RX_BD_M 0x0001
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//#define RX_BD_BC 0x8000
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//#define RX_BD_MC 0x4000
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//#define RX_BD_LG 0x2000
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//#define RX_BD_NO 0x1000
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//#define RX_BD_CR 0x0400
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//#define RX_BD_OV 0x0200
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//#define RX_BD_TR 0x0100
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//// ----------------------------------------------------------------------
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//// RX Enhanced BD Bit Definitions
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//// ----------------------------------------------------------------------
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//#define RX_BD_ME 0x00000080
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//#define RX_BD_PE 0x00000004
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//#define RX_BD_CE 0x00000002
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//#define RX_BD_UC 0x00000001
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//#define RX_BD_INT 0x00008000
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//#define RX_BD_ICE 0x20000000
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//#define RX_BD_PCR 0x10000000
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//#define RX_BD_VLAN 0x04000000
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//#define RX_BD_IPV6 0x02000000
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//#define RX_BD_FRAG 0x01000000
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//#define RX_BD_BDU 0x00000080
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///* MII Register Addresses */
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//#define PHY_BMCR (0x00)
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//#define PHY_BMSR (0x01)
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//#define PHY_PHYIDR1 (0x02)
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//#define PHY_PHYIDR2 (0x03)
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//#define PHY_ANAR (0x04)
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//#define PHY_ANLPAR (0x05)
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//#define PHY_ANLPARNP (0x05)
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//#define PHY_ANER (0x06)
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//#define PHY_ANNPTR (0x07)
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//#define PHY_PHYSTS (0x10)
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//#define PHY_MICR (0x11)
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//#define PHY_MISR (0x12)
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//#define PHY_PAGESEL (0x13)
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///*TSI-EVB definition: National Semiconductor*/
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//#define PHY_PHYCR2 (0x1C)
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///*TWR definition: Micrel*/
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//#define PHY_PHYCTRL1 (0x1E)
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//#define PHY_PHYCTRL2 (0x1F)
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///* Bit definitions and macros for PHY_BMCR */
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//#define PHY_BMCR_RESET (0x8000)
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//#define PHY_BMCR_LOOP (0x4000)
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//#define PHY_BMCR_SPEED (0x2000)
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//#define PHY_BMCR_AN_ENABLE (0x1000)
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//#define PHY_BMCR_POWERDOWN (0x0800)
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//#define PHY_BMCR_ISOLATE (0x0400)
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//#define PHY_BMCR_AN_RESTART (0x0200)
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//#define PHY_BMCR_FDX (0x0100)
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//#define PHY_BMCR_COL_TEST (0x0080)
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///* Bit definitions and macros for PHY_BMSR */
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//#define PHY_BMSR_100BT4 (0x8000)
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//#define PHY_BMSR_100BTX_FDX (0x4000)
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//#define PHY_BMSR_100BTX (0x2000)
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//#define PHY_BMSR_10BT_FDX (0x1000)
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//#define PHY_BMSR_10BT (0x0800)
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//#define PHY_BMSR_NO_PREAMBLE (0x0040)
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//#define PHY_BMSR_AN_COMPLETE (0x0020)
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//#define PHY_BMSR_REMOTE_FAULT (0x0010)
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//#define PHY_BMSR_AN_ABILITY (0x0008)
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//#define PHY_BMSR_LINK (0x0004)
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//#define PHY_BMSR_JABBER (0x0002)
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//#define PHY_BMSR_EXTENDED (0x0001)
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///* Bit definitions and macros for PHY_ANAR */
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//#define PHY_ANAR_NEXT_PAGE (0x8001)
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//#define PHY_ANAR_REM_FAULT (0x2001)
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//#define PHY_ANAR_PAUSE (0x0401)
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//#define PHY_ANAR_100BT4 (0x0201)
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//#define PHY_ANAR_100BTX_FDX (0x0101)
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//#define PHY_ANAR_100BTX (0x0081)
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//#define PHY_ANAR_10BT_FDX (0x0041)
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//#define PHY_ANAR_10BT (0x0021)
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//#define PHY_ANAR_802_3 (0x0001)
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///* Bit definitions and macros for PHY_ANLPAR */
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//#define PHY_ANLPAR_NEXT_PAGE (0x8000)
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//#define PHY_ANLPAR_ACK (0x4000)
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//#define PHY_ANLPAR_REM_FAULT (0x2000)
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//#define PHY_ANLPAR_PAUSE (0x0400)
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//#define PHY_ANLPAR_100BT4 (0x0200)
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//#define PHY_ANLPAR_100BTX_FDX (0x0100)
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//#define PHY_ANLPAR_100BTX (0x0080)
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//#define PHY_ANLPAR_10BTX_FDX (0x0040)
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//#define PHY_ANLPAR_10BT (0x0020)
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///* Bit definitions of PHY_PHYSTS: National */
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//#define PHY_PHYSTS_MDIXMODE (0x4000)
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//#define PHY_PHYSTS_RX_ERR_LATCH (0x2000)
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//#define PHY_PHYSTS_POL_STATUS (0x1000)
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//#define PHY_PHYSTS_FALSECARRSENSLAT (0x0800)
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//#define PHY_PHYSTS_SIGNALDETECT (0x0400)
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//#define PHY_PHYSTS_PAGERECEIVED (0x0100)
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//#define PHY_PHYSTS_MIIINTERRUPT (0x0080)
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//#define PHY_PHYSTS_REMOTEFAULT (0x0040)
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//#define PHY_PHYSTS_JABBERDETECT (0x0020)
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//#define PHY_PHYSTS_AUTONEGCOMPLETE (0x0010)
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//#define PHY_PHYSTS_LOOPBACKSTATUS (0x0008)
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//#define PHY_PHYSTS_DUPLEXSTATUS (0x0004)
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//#define PHY_PHYSTS_SPEEDSTATUS (0x0002)
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//#define PHY_PHYSTS_LINKSTATUS (0x0001)
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///* Bit definitions of PHY_PHYCR2 */
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//#define PHY_PHYCR2_SYNC_ENET_EN (0x2000)
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//#define PHY_PHYCR2_CLK_OUT_RXCLK (0x1000)
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//#define PHY_PHYCR2_BC_WRITE (0x0800)
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//#define PHY_PHYCR2_PHYTER_COMP (0x0400)
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//#define PHY_PHYCR2_SOFT_RESET (0x0200)
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//#define PHY_PHYCR2_CLK_OUT_DIS (0x0001)
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///* Bit definition and macros for PHY_PHYCTRL1 */
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//#define PHY_PHYCTRL1_LED_MASK (0xC000)
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//#define PHY_PHYCTRL1_POLARITY (0x2000)
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//#define PHY_PHYCTRL1_MDX_STATE (0x0800)
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//#define PHY_PHYCTRL1_REMOTE_LOOP (0x0080)
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///* Bit definition and macros for PHY_PHYCTRL2 */
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//#define PHY_PHYCTRL2_HP_MDIX (0x8000)
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//#define PHY_PHYCTRL2_MDIX_SELECT (0x4000)
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//#define PHY_PHYCTRL2_PAIRSWAP_DIS (0x2000)
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//#define PHY_PHYCTRL2_ENERGY_DET (0x1000)
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//#define PHY_PHYCTRL2_FORCE_LINK (0x0800)
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//#define PHY_PHYCTRL2_POWER_SAVING (0x0400)
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//#define PHY_PHYCTRL2_INT_LEVEL (0x0200)
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//#define PHY_PHYCTRL2_EN_JABBER (0x0100)
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//#define PHY_PHYCTRL2_AUTONEG_CMPLT (0x0080)
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//#define PHY_PHYCTRL2_ENABLE_PAUSE (0x0040)
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//#define PHY_PHYCTRL2_PHY_ISOLATE (0x0020)
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//#define PHY_PHYCTRL2_OP_MOD_MASK (0x001C)
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//#define PHY_PHYCTRL2_EN_SQE_TEST (0x0002)
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//#define PHY_PHYCTRL2_DATA_SCRAM_DIS (0x0001)
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///* Bit definitions of PHY_PHYCTRL2_OP_MOD_MASK */
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//#define PHY_PHYCTRL2_OP_MOD_SHIFT 2
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//#define PHY_PHYCTRL2_MODE_OP_MOD_STILL_NEG 0
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//#define PHY_PHYCTRL2_MODE_OP_MOD_10MBPS_HD 1
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//#define PHY_PHYCTRL2_MODE_OP_MOD_100MBPS_HD 2
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//#define PHY_PHYCTRL2_MODE_OP_MOD_10MBPS_FD 5
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//#define PHY_PHYCTRL2_MODE_OP_MOD_100MBPS_FD 6
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//#define MII_TIMEOUT 0x1FF
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//#define MII_LINK_TIMEOUT 0x1FF
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//int drv_emac_hw_init(void);
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#endif
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