74 lines
1.7 KiB
C
74 lines
1.7 KiB
C
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2023-10-18 shelton first version
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*/
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#include "board.h"
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void system_clock_config(void)
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{
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/* reset crm */
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crm_reset();
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/* config flash psr register */
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flash_psr_set(FLASH_WAIT_CYCLE_6);
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/* enable pwc periph clock */
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crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE);
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/* set power ldo output voltage to 1.3v */
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pwc_ldo_output_voltage_set(PWC_LDO_OUTPUT_1V3);
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crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE);
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/* wait till hext is ready */
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while(crm_hext_stable_wait() == ERROR)
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{
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}
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/* if pll parameter has changed, please use the AT32_New_Clock_Configuration tool for new configuration. */
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crm_pll_config(CRM_PLL_SOURCE_HEXT, 72, 1, CRM_PLL_FP_4);
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/* config pllu div */
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crm_pllu_div_set(CRM_PLL_FU_18);
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/* enable pll */
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crm_clock_source_enable(CRM_CLOCK_SOURCE_PLL, TRUE);
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/* wait till pll is ready */
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while(crm_flag_get(CRM_PLL_STABLE_FLAG) != SET)
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{
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}
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/* config ahbclk */
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crm_ahb_div_set(CRM_AHB_DIV_1);
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/* config apb2clk, the maximum frequency of APB2 clock is 216 MHz */
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crm_apb2_div_set(CRM_APB2_DIV_1);
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/* config apb1clk, the maximum frequency of APB1 clock is 120 MHz */
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crm_apb1_div_set(CRM_APB1_DIV_2);
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/* enable auto step mode */
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crm_auto_step_mode_enable(TRUE);
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/* select pll as system clock source */
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crm_sysclk_switch(CRM_SCLK_PLL);
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/* wait till pll is used as system clock source */
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while(crm_sysclk_switch_status_get() != CRM_SCLK_PLL)
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{
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}
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/* disable auto step mode */
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crm_auto_step_mode_enable(FALSE);
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/* update system_core_clock global variable */
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system_core_clock_update();
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}
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