84 lines
2.6 KiB
C
84 lines
2.6 KiB
C
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/*
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* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2023-03-01 CDT first version
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*/
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#ifndef __NAND_PORT_H__
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#define __NAND_PORT_H__
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/******************** NAND chip information ***********************************/
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#define NAND_BYTES_PER_PAGE 2048UL
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#define NAND_SPARE_AREA_SIZE 64UL
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#define NAND_PAGES_PER_BLOCK 64UL
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#define NAND_BYTES_PER_BLOCK (NAND_PAGES_PER_BLOCK * NAND_BYTES_PER_PAGE)
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#define NAND_BLOCKS_PER_PLANE 1024UL
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#define NAND_PLANE_PER_DEVICE 2UL
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#define NAND_DEVICE_BLOCKS (NAND_BLOCKS_PER_PLANE * NAND_PLANE_PER_DEVICE)
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#define NAND_DEVICE_PAGES (NAND_DEVICE_BLOCKS * NAND_PAGES_PER_BLOCK)
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/******************** EXMC_NFC configure **************************************/
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/* chip: EXMC_NFC_BANK0~7 */
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#define NAND_EXMC_NFC_BANK EXMC_NFC_BANK0
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/* density:2Gbit */
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#define NAND_EXMC_NFC_BANK_CAPACITY EXMC_NFC_BANK_CAPACITY_2GBIT
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/* device width: 8-bit */
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#define NAND_EXMC_NFC_MEMORY_WIDTH EXMC_NFC_MEMORY_WIDTH_8BIT
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/* page size: 2KByte */
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#define NAND_EXMC_NFC_PAGE_SIZE EXMC_NFC_PAGE_SIZE_2KBYTE
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/* row address cycle: 3 */
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#define NAND_EXMC_NFC_ROW_ADDR_CYCLE EXMC_NFC_3_ROW_ADDR_CYCLE
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/* ECC mode */
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#define NAND_EXMC_NFC_ECC_MD EXMC_NFC_1BIT_ECC
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/* timing configuration(EXCLK clock frequency: 60MHz@3.3V) for MT29F2G08AB */
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/* TS: ALE/CLE/CE setup time(min=10ns) */
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#define NAND_TS 1U
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/* TWP: WE# pulse width (min=10ns) */
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#define NAND_TWP 1U
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/* TRP: RE# pulse width (MT29F2G08AB min=10ns and EXMC t_data_s min=24ns) */
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#define NAND_TRP 2U
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/* TTH: ALE/CLE/CE hold time (min=5ns) */
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#define NAND_TH 1U
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/* TWH: WE# pulse width HIGH (min=10ns) */
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#define NAND_TWH 1U
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/* TRH: RE# pulse width HIGH (min=7ns) */
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#define NAND_TRH 1U
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/* TRR: Ready to RE# LOW (min=20ns) */
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#define NAND_TRR 2U
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/* TWB: WE# HIGH to busy (max=100ns) */
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#define NAND_TWB 1U
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/* TWB: WE# HIGH to busy (max=100ns) */
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#define NAND_TRB 1U
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/* TCCS: Change read column and Change write column delay */
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#define NAND_TCCS 5U
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/* TWTR: WE# HIGH to RE# LOW (min=60ns) */
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#define NAND_TWTR 4U
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/* TRTW: RE# HIGH to WE# LOW (min=100ns) */
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#define NAND_TRTW 7U
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/* TADL: ALE to data start (min=70ns) */
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#define NAND_TADL 5U
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#endif
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