306 lines
7.0 KiB
C
306 lines
7.0 KiB
C
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Email: opensource_embedded@phytium.com.cn
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*
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* Change Logs:
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* Date Author Notes
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* 2022-10-26 huanghe first commit
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* 2022-10-26 zhugengyu support aarch64
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*
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*/
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#include "rtconfig.h"
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#include <rthw.h>
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#include <rtthread.h>
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#include <mmu.h>
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#include <gicv3.h>
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#if defined(TARGET_ARMV8_AARCH64)
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#include <psci.h>
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#include <gtimer.h>
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#include <cpuport.h>
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#else
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#include "fgeneric_timer.h" /* for aarch32 */
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#endif
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#include <interrupt.h>
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#include <board.h>
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#include "fdebug.h"
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#include "fprintk.h"
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#include "fearly_uart.h"
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#include "fcpu_info.h"
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#include "fpsci.h"
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#define LOG_DEBUG_TAG "BOARD"
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#define BSP_LOG_ERROR(format, ...) FT_DEBUG_PRINT_E(LOG_DEBUG_TAG, format, ##__VA_ARGS__)
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#define BSP_LOG_WARN(format, ...) FT_DEBUG_PRINT_W(LOG_DEBUG_TAG, format, ##__VA_ARGS__)
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#define BSP_LOG_INFO(format, ...) FT_DEBUG_PRINT_I(LOG_DEBUG_TAG, format, ##__VA_ARGS__)
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#define BSP_LOG_DEBUG(format, ...) FT_DEBUG_PRINT_D(LOG_DEBUG_TAG, format, ##__VA_ARGS__)
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/* mmu config */
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struct mem_desc platform_mem_desc[] =
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#if defined(TARGET_E2000)
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{
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{
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0x00U,
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0x00U + 0x40000000U,
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0x00U,
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DEVICE_MEM
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},
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{
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0x40000000U,
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0x40000000U + 0x10000000U,
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0x40000000U,
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DEVICE_MEM
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},
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{
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0x50000000U,
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0x50000000U + 0x30000000U,
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0x50000000U,
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DEVICE_MEM
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},
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{
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0x80000000U,
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0xffffffffU,
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0x80000000U,
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NORMAL_MEM
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},
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#if defined(TARGET_ARMV8_AARCH64)
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{
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0x1000000000,
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0x1000000000 + 0x1000000000,
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0x1000000000,
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DEVICE_MEM
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},
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{
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0x2000000000,
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0x2000000000 + 0x2000000000,
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0x2000000000,
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NORMAL_MEM
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},
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#endif
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};
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#elif defined(TARGET_F2000_4) || defined(TARGET_D2000)
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{
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{
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0x80000000,
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0xFFFFFFFF,
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0x80000000,
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DDR_MEM
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},
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{
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0, //< QSPI
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0x1FFFFFFF,
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0,
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DEVICE_MEM
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},
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{
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0x20000000, //<! LPC
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0x27FFFFFF,
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0x20000000,
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DEVICE_MEM
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},
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{
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FT_DEV_BASE_ADDR, //<! Device register
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FT_DEV_END_ADDR,
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FT_DEV_BASE_ADDR,
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DEVICE_MEM
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},
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{
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0x30000000, //<! debug
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0x39FFFFFF,
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0x30000000,
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DEVICE_MEM
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},
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{
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0x3A000000, //<! Internal register space in the on-chip network
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0x3AFFFFFF,
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0x3A000000,
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DEVICE_MEM
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},
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{
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FT_PCI_CONFIG_BASEADDR,
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FT_PCI_CONFIG_BASEADDR + FT_PCI_CONFIG_REG_LENGTH,
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FT_PCI_CONFIG_BASEADDR,
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DEVICE_MEM
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},
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{
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FT_PCI_IO_CONFIG_BASEADDR,
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FT_PCI_IO_CONFIG_BASEADDR + FT_PCI_IO_CONFIG_REG_LENGTH,
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FT_PCI_IO_CONFIG_BASEADDR,
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DEVICE_MEM
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},
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{
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FT_PCI_MEM32_BASEADDR,
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FT_PCI_MEM32_BASEADDR + FT_PCI_MEM32_REG_LENGTH,
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FT_PCI_MEM32_BASEADDR,
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DEVICE_MEM
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}
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#if defined(TARGET_ARMV8_AARCH64)
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{
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0x1000000000,
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0x1000000000 + 0x1000000000,
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0x1000000000,
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DEVICE_MEM
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},
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{
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0x2000000000,
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0x2000000000 + 0x2000000000,
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0x2000000000,
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NORMAL_MEM
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},
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#endif
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};
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#endif
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const rt_uint32_t platform_mem_desc_size = sizeof(platform_mem_desc) / sizeof(platform_mem_desc[0]);
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#if defined(TARGET_ARMV8_AARCH64) /* AARCH64 */
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/* aarch64 use kernel gtimer */
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void idle_wfi(void)
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{
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asm volatile("wfi");
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}
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#else /* AARCH32 */
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static rt_uint32_t timerStep;
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void rt_hw_timer_isr(int vector, void *parameter)
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{
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GenericTimerCompare(timerStep);
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rt_tick_increase();
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}
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int rt_hw_timer_init(void)
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{
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rt_hw_interrupt_install(GENERIC_TIMER_NS_IRQ_NUM, rt_hw_timer_isr, RT_NULL, "tick");
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rt_hw_interrupt_umask(GENERIC_TIMER_NS_IRQ_NUM);
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timerStep = GenericTimerFrequecy();
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timerStep /= RT_TICK_PER_SECOND;
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GenericTimerCompare(timerStep);
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GenericTimerInterruptEnable();
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GenericTimerStart();
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return 0;
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}
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INIT_BOARD_EXPORT(rt_hw_timer_init);
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#endif
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#ifdef RT_USING_SMP
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void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler);
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#endif
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/**
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* This function will initialize hardware board
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*/
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void rt_hw_board_init(void)
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{
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/* mmu init */
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#if defined(TARGET_ARMV8_AARCH64)
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rt_hw_init_mmu_table(platform_mem_desc, platform_mem_desc_size);
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rt_hw_mmu_init();
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#endif
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/* interrupt init */
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#if defined(TARGET_ARMV8_AARCH64)
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f_printk("aarch64 interrupt init \r\n");
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#else
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f_printk("aarch32 interrupt init \r\n");
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extern int rt_hw_cpu_id(void);
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u32 cpu_id, cpu_offset = 0;
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GetCpuId(&cpu_id);
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f_printk("cpu_id is %d \r\n", cpu_id);
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#if defined(FT_GIC_REDISTRUBUTIOR_OFFSET)
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cpu_offset = FT_GIC_REDISTRUBUTIOR_OFFSET ;
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#endif
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f_printk("cpu_offset is %d \r\n", cpu_offset);
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arm_gic_redist_address_set(0, GICV3_RD_BASEADDRESS + (cpu_id + cpu_offset) * GICV3_RD_OFFSET, rt_hw_cpu_id());
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#if defined(TARGET_E2000Q)
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#if RT_CPUS_NR == 2
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f_printk("arm_gic_redist_address_set is 2 \r\n");
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arm_gic_redist_address_set(0, GICV3_RD_BASEADDRESS + 3 * GICV3_RD_OFFSET, 1);
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#elif RT_CPUS_NR == 3
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arm_gic_redist_address_set(0, GICV3_RD_BASEADDRESS + 3 * GICV3_RD_OFFSET, 1);
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arm_gic_redist_address_set(0, GICV3_RD_BASEADDRESS, 2);
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#elif RT_CPUS_NR == 4
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arm_gic_redist_address_set(0, GICV3_RD_BASEADDRESS + 3 * GICV3_RD_OFFSET, 1);
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arm_gic_redist_address_set(0, GICV3_RD_BASEADDRESS, 2);
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arm_gic_redist_address_set(0, GICV3_RD_BASEADDRESS + GICV3_RD_OFFSET, 3);
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#endif
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#else
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#if RT_CPUS_NR == 2
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f_printk("arm_gic_redist_address_set is 2 \r\n");
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arm_gic_redist_address_set(0, GICV3_RD_BASEADDRESS + (1 + cpu_offset) * GICV3_RD_OFFSET, 1);
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#elif RT_CPUS_NR == 3
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arm_gic_redist_address_set(0, GICV3_RD_BASEADDRESS + (1 + cpu_offset) * GICV3_RD_OFFSET, 1);
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arm_gic_redist_address_set(0, GICV3_RD_BASEADDRESS + (2 + cpu_offset) * GICV3_RD_OFFSET, 2);
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#elif RT_CPUS_NR == 4
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arm_gic_redist_address_set(0, GICV3_RD_BASEADDRESS + (1 + cpu_offset) * GICV3_RD_OFFSET, 1);
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arm_gic_redist_address_set(0, GICV3_RD_BASEADDRESS + (2 + cpu_offset) * GICV3_RD_OFFSET, 2);
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arm_gic_redist_address_set(0, GICV3_RD_BASEADDRESS + (3 + cpu_offset) * GICV3_RD_OFFSET, 3);
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#endif
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#endif
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#endif
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rt_hw_interrupt_init();
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/* gtimer init */
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#if defined(TARGET_ARMV8_AARCH64)
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rt_hw_gtimer_init();
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#endif
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/* compoent init */
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#ifdef RT_USING_COMPONENTS_INIT
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rt_components_board_init();
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#endif
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/* shell init */
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#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
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/* set console device */
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rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
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#endif
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/* init memory pool */
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#ifdef RT_USING_HEAP
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rt_system_heap_init(HEAP_BEGIN, HEAP_END);
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#endif
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#ifdef RT_USING_SMP
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/* install IPI handle */
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rt_hw_interrupt_set_priority(RT_SCHEDULE_IPI, 16);
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rt_hw_ipi_handler_install(RT_SCHEDULE_IPI, rt_scheduler_ipi_handler);
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rt_hw_interrupt_umask(RT_SCHEDULE_IPI);
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#endif
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}
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static void ft_reset(void)
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{
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PsciCpuReset();
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}
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MSH_CMD_EXPORT_ALIAS(ft_reset, ft_reset, ft_reset);
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/*@}*/
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