102 lines
5.9 KiB
C
102 lines
5.9 KiB
C
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/*
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* Copyright 2020-2021 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/***********************************************************************************************************************
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* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
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* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
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**********************************************************************************************************************/
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/*
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* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!GlobalInfo
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product: Pins v9.0
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processor: MIMXRT1176xxxxx
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package_id: MIMXRT1176DVMAA
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mcu_data: ksdk2_0
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processor_version: 0.9.6
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
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*/
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#include "fsl_common.h"
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#include "fsl_iomuxc.h"
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#include "pin_mux.h"
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/* FUNCTION ************************************************************************************************************
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*
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* Function Name : BOARD_InitBootPins
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* Description : Calls initialization functions.
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*
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* END ****************************************************************************************************************/
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void BOARD_InitBootPins(void) {
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BOARD_InitPins();
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}
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/*
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* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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BOARD_InitPins:
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- options: {callFromInitBoot: 'true', coreID: cm7, enableClock: 'true'}
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- pin_list:
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- {pin_num: M15, peripheral: LPUART1, signal: RXD, pin_signal: GPIO_AD_25, software_input_on: Disable, pull_up_down_config: Pull_Down, pull_keeper_select: Keeper,
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open_drain: Disable, drive_strength: High, slew_rate: Slow}
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- {pin_num: L13, peripheral: LPUART1, signal: TXD, pin_signal: GPIO_AD_24, software_input_on: Disable, pull_up_down_config: Pull_Down, pull_keeper_select: Keeper,
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open_drain: Disable, drive_strength: High, slew_rate: Slow}
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- {pin_num: D6, peripheral: ARM, signal: arm_trace_swo, pin_signal: GPIO_DISP_B2_07, software_input_on: Disable, pull_up_down_config: Pull_Down, pull_keeper_select: Keeper,
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open_drain: Disable, drive_strength: High, slew_rate: Slow}
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
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*/
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/* FUNCTION ************************************************************************************************************
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*
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* Function Name : BOARD_InitPins, assigned for the Cortex-M7F core.
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* Description : Configures pin routing and optionally pin electrical features.
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*
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* END ****************************************************************************************************************/
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void BOARD_InitPins(void) {
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CLOCK_EnableClock(kCLOCK_Iomuxc); /* LPCG on: LPCG is ON. */
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_AD_24_LPUART1_TXD, /* GPIO_AD_24 is configured as LPUART1_TXD */
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0U); /* Software Input On Field: Input Path is determined by functionality */
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_AD_25_LPUART1_RXD, /* GPIO_AD_25 is configured as LPUART1_RXD */
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0U); /* Software Input On Field: Input Path is determined by functionality */
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_DISP_B2_07_ARM_TRACE_SWO, /* GPIO_DISP_B2_07 is configured as ARM_TRACE_SWO */
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0U); /* Software Input On Field: Input Path is determined by functionality */
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IOMUXC_SetPinConfig(
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IOMUXC_GPIO_AD_24_LPUART1_TXD, /* GPIO_AD_24 PAD functional properties : */
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0x02U); /* Slew Rate Field: Slow Slew Rate
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Drive Strength Field: high drive strength
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Pull / Keep Select Field: Pull Disable, Highz
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Pull Up / Down Config. Field: Weak pull down
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Open Drain Field: Disabled
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Domain write protection: Both cores are allowed
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Domain write protection lock: Neither of DWP bits is locked */
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IOMUXC_SetPinConfig(
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IOMUXC_GPIO_AD_25_LPUART1_RXD, /* GPIO_AD_25 PAD functional properties : */
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0x02U); /* Slew Rate Field: Slow Slew Rate
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Drive Strength Field: high drive strength
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Pull / Keep Select Field: Pull Disable, Highz
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Pull Up / Down Config. Field: Weak pull down
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Open Drain Field: Disabled
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Domain write protection: Both cores are allowed
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Domain write protection lock: Neither of DWP bits is locked */
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IOMUXC_SetPinConfig(
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IOMUXC_GPIO_DISP_B2_07_ARM_TRACE_SWO, /* GPIO_DISP_B2_07 PAD functional properties : */
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0x02U); /* Slew Rate Field: Slow Slew Rate
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Drive Strength Field: high drive strength
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Pull / Keep Select Field: Pull Disable, Highz
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Pull Up / Down Config. Field: Weak pull down
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Open Drain Field: Disabled
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Domain write protection: Both cores are allowed
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Domain write protection lock: Neither of DWP bits is locked */
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}
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/***********************************************************************************************************************
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* EOF
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**********************************************************************************************************************/
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