291 lines
19 KiB
C
291 lines
19 KiB
C
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////////////////////////////////////////////////////////////////////////////////
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/// @file reg_flash.h
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/// @author AE TEAM
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/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
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/// MM32 FIRMWARE LIBRARY.
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////////////////////////////////////////////////////////////////////////////////
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/// @attention
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///
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/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
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/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
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/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
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/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
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/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
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/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
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///
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/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
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////////////////////////////////////////////////////////////////////////////////
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// Define to prevent recursive inclusion
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#ifndef __REG_FLASH_H
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#define __REG_FLASH_H
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// Files includes
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#include <stdint.h>
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#include <stdbool.h>
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#include "types.h"
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#if defined ( __CC_ARM )
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#pragma anon_unions
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#endif
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////////////////////////////////////////////////////////////////////////////////
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/// @brief MM32 MCU Memory/Peripherals mapping
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////////////////////////////////////////////////////////////////////////////////
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#define FLASH_BASE (0x08000000U) ///< FLASH base address in the alias region
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#define SRAM_BASE (0x20000000U) ///< SRAM base address in the alias region
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#define CACHE_BASE (APB2PERIPH_BASE + 0x6000) ///< Base Address: 0x40016000
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////////////////////////////////////////////////////////////////////////////////
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/// @brief FLASH Base Address Definition
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////////////////////////////////////////////////////////////////////////////////
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#define FLASH_REG_BASE (AHBPERIPH_BASE + 0x2000) ///< Base Address: 0x40022000
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////////////////////////////////////////////////////////////////////////////////
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/// @brief OPTB Base Address Definition
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////////////////////////////////////////////////////////////////////////////////
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#define OB_BASE (0x1FFFF800U) ///< Flash Option Bytes base address
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#define PROTECT_BASE (0x1FFE0000U) ///< Flash Protect Bytes base address
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////////////////////////////////////////////////////////////////////////////////
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/// @brief FLASH Registers Structure Definition
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////////////////////////////////////////////////////////////////////////////////
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typedef struct {
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__IO u32 ACR; ///< Access control Register offset: 0x00
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__IO u32 KEYR; ///< Key Register offset: 0x04
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__IO u32 OPTKEYR; ///< Option byte key Register offset: 0x08
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__IO u32 SR; ///< State Register offset: 0x0C
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__IO u32 CR; ///< Control Register offset: 0x10
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__IO u32 AR; ///< Address Register offset: 0x14
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__IO u32 RESERVED;
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__IO u32 OBR; ///< Option bytes Register offset: 0x1C
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__IO u32 WRPR; ///< Write protect Register offset: 0x20
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} FLASH_TypeDef;
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////////////////////////////////////////////////////////////////////////////////
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/// @brief OPT Structure Definition
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////////////////////////////////////////////////////////////////////////////////
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typedef struct {
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__IO u16 RDP; ///< Read Protect, offset: 0x00
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__IO u16 USER; ///< User option byte, offset: 0x02
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__IO u16 Data0; ///< User data 0, offset: 0x04
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__IO u16 Data1; ///< User data 1, offset: 0x06
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__IO u16 WRP0; ///< Flash write protection option byte 0, offset: 0x08
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__IO u16 WRP1; ///< Flash write protection option byte 1, offset: 0x0A
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__IO u16 WRP2; ///< Flash write protection option byte 2, offset: 0x0C
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__IO u16 WRP3; ///< Flash write protection option byte 3, offset: 0x0E
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} OB_TypeDef;
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////////////////////////////////////////////////////////////////////////////////
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/// @brief PROTECT BYTES Structure Definition
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////////////////////////////////////////////////////////////////////////////////
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typedef struct {
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__IO u16 PROTECT_LEN0; ///< The length of Protect byte 0, offset: 0x00
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__IO u16 PROTECT_ADDR0; ///< Data of Protect byte 0, offset: 0x02
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__IO u16 PROTECT_LEN1; ///< The length of Protect byte 1, offset: 0x04
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__IO u16 PROTECT_ADDR1; ///< Data of Protect byte 1, offset: 0x06
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__IO u16 PROTECT_LEN2; ///< The length of Protect byte 2, offset: 0x08
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__IO u16 PROTECT_ADDR2; ///< Data of Protect byte 2, offset: 0x0A
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__IO u16 PROTECT_LEN3; ///< The length of Protect byte 3, offset: 0x0C
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__IO u16 PROTECT_ADDR3; ///< Data of Protect byte 3, offset: 0x0E
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} PROTECT_TypeDef;
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////////////////////////////////////////////////////////////////////////////////
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/// @brief CACHE BYTES Structure Definition
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////////////////////////////////////////////////////////////////////////////////
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typedef struct {
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__IO u32 CCR; ///< Configuration and control register offset: 0x00
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__IO u32 SR; ///< Status register offset: 0x04
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__IO u32 IMR; ///< Interrupt mask register offset: 0x08
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__IO u32 ISR; ///< Interrupt status register offset: 0x0C
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__IO u32 RESERVED0; ///< offset: 0x10
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__IO u32 CSHR; ///< Hit Statistics Register offset: 0x14
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__IO u32 CSMR; ///< Lost Statistics Register offset: 0x18
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} CACHE_TypeDef;
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////////////////////////////////////////////////////////////////////////////////
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/// @brief FLASH type pointer Definition
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////////////////////////////////////////////////////////////////////////////////
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#define FLASH ((FLASH_TypeDef*) FLASH_REG_BASE)
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////////////////////////////////////////////////////////////////////////////////
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/// @brief OPTB type pointer Definition
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////////////////////////////////////////////////////////////////////////////////
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#define OB ((OB_TypeDef*) OB_BASE)
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#define PROTECT ((PROTECT_TypeDef*) PROTECT_BASE)
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////////////////////////////////////////////////////////////////////////////////
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/// @brief CACHE pointer Definition
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////////////////////////////////////////////////////////////////////////////////
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#define CACHE ((CACHE_TypeDef*) CACHE_BASE)
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////////////////////////////////////////////////////////////////////////////////
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/// @brief FLASH_ACR Register Bit Definition
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////////////////////////////////////////////////////////////////////////////////
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#define FLASH_ACR_LATENCY_Pos (0)
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#define FLASH_ACR_LATENCY (0x07U << FLASH_ACR_LATENCY_Pos) ///< LATENCY[2:0] bits (Latency)
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#define FLASH_ACR_LATENCY_0 (0x00U << FLASH_ACR_LATENCY_Pos) ///< 0 waiting state
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#define FLASH_ACR_LATENCY_1 (0x01U << FLASH_ACR_LATENCY_Pos) ///< 1 waiting state
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#define FLASH_ACR_LATENCY_2 (0x02U << FLASH_ACR_LATENCY_Pos) ///< 2 waiting state
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#define FLASH_ACR_LATENCY_3 (0x03U << FLASH_ACR_LATENCY_Pos) ///< 3 waiting state
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#define FLASH_ACR_HLFCYA_Pos (3)
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#define FLASH_ACR_HLFCYA (0x01U << FLASH_ACR_HLFCYA_Pos) ///< Flash Half Cycle Access Enable
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#define FLASH_ACR_PRFTBE_Pos (4)
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#define FLASH_ACR_PRFTBE (0x01U << FLASH_ACR_PRFTBE_Pos) ///< Prefetch Buffer Enable
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#define FLASH_ACR_PRFTBS_Pos (5)
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#define FLASH_ACR_PRFTBS (0x01U << FLASH_ACR_PRFTBS_Pos) ///< Prefetch Buffer Status
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////////////////////////////////////////////////////////////////////////////////
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/// @brief FLASH_KEYR Register Bit Definition
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////////////////////////////////////////////////////////////////////////////////
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#define FLASH_KEYR_FKEY_Pos (0)
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#define FLASH_KEYR_FKEY (0xFFFFFFFFU << FLASH_KEYR_FKEY_Pos) ///< FLASH Key
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////////////////////////////////////////////////////////////////////////////////
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/// @brief FLASH_OPTKEYR Register Bit Definition
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////////////////////////////////////////////////////////////////////////////////
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#define FLASH_OPTKEYR_OPTKEY_Pos (0)
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#define FLASH_OPTKEYR_OPTKEY (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEY_Pos) ///< Option Byte Key
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////////////////////////////////////////////////////////////////////////////////
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/// @brief FLASH_SR Register Bit Definition
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////////////////////////////////////////////////////////////////////////////////
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#define FLASH_SR_BUSY_Pos (0)
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#define FLASH_SR_BUSY (0x01U << FLASH_SR_BUSY_Pos) ///< Busy
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#define FLASH_SR_PGERR_Pos (2)
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#define FLASH_SR_PGERR (0x01U << FLASH_SR_PGERR_Pos) ///< Programming Error
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#define FLASH_SR_WRPRTERR_Pos (4)
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#define FLASH_SR_WRPRTERR (0x01U << FLASH_SR_WRPRTERR_Pos) ///< Write Protection Error
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#define FLASH_SR_EOP_Pos (5)
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#define FLASH_SR_EOP (0x01U << FLASH_SR_EOP_Pos) ///< End of operation
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////////////////////////////////////////////////////////////////////////////////
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/// @brief FLASH_CR Register Bit Definition
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////////////////////////////////////////////////////////////////////////////////
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#define FLASH_CR_PG_Pos (0)
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#define FLASH_CR_PG (0x01U << FLASH_CR_PG_Pos) ///< Programming
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#define FLASH_CR_PER_Pos (1)
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#define FLASH_CR_PER (0x01U << FLASH_CR_PER_Pos) ///< Page Erase
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#define FLASH_CR_MER_Pos (2)
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#define FLASH_CR_MER (0x01U << FLASH_CR_MER_Pos) ///< Mass Erase
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#define FLASH_CR_OPTPG_Pos (4)
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#define FLASH_CR_OPTPG (0x01U << FLASH_CR_OPTPG_Pos) ///< Option Byte Programming
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#define FLASH_CR_OPTER_Pos (5)
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#define FLASH_CR_OPTER (0x01U << FLASH_CR_OPTER_Pos) ///< Option Byte Erase
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#define FLASH_CR_STRT_Pos (6)
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#define FLASH_CR_STRT (0x01U << FLASH_CR_STRT_Pos) ///< Start
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#define FLASH_CR_LOCK_Pos (7)
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#define FLASH_CR_LOCK (0x01U << FLASH_CR_LOCK_Pos) ///< Lock
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#define FLASH_CR_OPTWRE_Pos (9)
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#define FLASH_CR_OPTWRE (0x01U << FLASH_CR_OPTWRE_Pos) ///< Option Bytes Write Enable
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#define FLASH_CR_ERRIE_Pos (10)
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#define FLASH_CR_ERRIE (0x01U << FLASH_CR_ERRIE_Pos) ///< Error Interrupt Enable
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#define FLASH_CR_EOPIE_Pos (12)
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#define FLASH_CR_EOPIE (0x01U << FLASH_CR_EOPIE_Pos) ///< End of operation interrupt enable
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////////////////////////////////////////////////////////////////////////////////
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/// @brief FLASH_AR Register Bit Definition
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////////////////////////////////////////////////////////////////////////////////
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#define FLASH_AR_FAR_Pos (0)
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#define FLASH_AR_FAR (0xFFFFFFFFU << FLASH_AR_FAR_Pos) ///< Flash Address
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////////////////////////////////////////////////////////////////////////////////
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/// @brief FLASH_OBR Register Bit Definition
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////////////////////////////////////////////////////////////////////////////////
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#define FLASH_OBR_OPTERR_Pos (0)
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#define FLASH_OBR_OPTERR (0x01U << FLASH_OBR_OPTERR_Pos) ///< Option Byte Error
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#define FLASH_OBR_RDPRT_Pos (1)
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#define FLASH_OBR_RDPRT (0x01U << FLASH_OBR_RDPRT_Pos) ///< Read protection level status
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#define FLASH_OBR_USER_Pos (2)
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#define FLASH_OBR_USER (0xFFU << FLASH_OBR_USER_Pos) ///< User Option Bytes
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#define FLASH_OBR_WDG_SW (0x01U << FLASH_OBR_USER_Pos) ///< WDG_SW
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#define FLASH_OBR_RST_STOP (0x02U << FLASH_OBR_USER_Pos) ///< nRST_STOP
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#define FLASH_OBR_RST_STDBY (0x04U << FLASH_OBR_USER_Pos) ///< nRST_STDBY
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#define FLASH_OBR_Data0_Pos (10)
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#define FLASH_OBR_Data0 (0xFFU << FLASH_OBR_Data0_Pos) ///< User data storage option byte
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#define FLASH_OBR_Data1_Pos (18)
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#define FLASH_OBR_Data1 (0xFFU << FLASH_OBR_Data1_Pos) ///< User data storage option byte
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////////////////////////////////////////////////////////////////////////////////
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/// @brief FLASH_WRPR Register Bit Definition
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////////////////////////////////////////////////////////////////////////////////
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#define FLASH_WRPR_WRP_Pos (0)
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#define FLASH_WRPR_WRP (0xFFFFFFFFU << FLASH_WRPR_WRP_Pos) ///< Write Protect
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////////////////////////////////////////////////////////////////////////////////
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/// @brief CACHE_CCR Register Bit Definition
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////////////////////////////////////////////////////////////////////////////////
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#define CACHE_CCR_EN_Pos (0)
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#define CACHE_CCR_EN (0x01U << CACHE_CCR_EN_Pos) ///< Cache Enable
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#define CACHE_CCR_INV_Pos (1)
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#define CACHE_CCR_INV (0x01U << CACHE_CCR_INV_REQ_Pos) ///< Manually invalidate the request
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#define CACHE_CCR_POW_Pos (2)
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#define CACHE_CCR_POW (0x01U << CACHE_CCR_POW_REQ_Pos) ///< Manual SRAM power request
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#define CACHE_CCR_MAN_POW_Pos (3)
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#define CACHE_CCR_MAN_POW (0x01U << CACHE_CCR_MAN_POW_Pos) ///< Set manual or automatic SRAM power request
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#define CACHE_CCR_MAN_INV_Pos (4)
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#define CACHE_CCR_MAN_INV (0x01U << CACHE_CCR_MAN_INV_Pos) ///< Manually or automatically disable it
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#define CACHE_CCR_PREFETCH_Pos (5)
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#define CACHE_CCR_PREFETCH (0x01U << CACHE_CCR_PREFETCH_Pos) ///< Prefetch function
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#define CACHE_CCR_STATISTIC_Pos (6)
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#define CACHE_CCR_STATISTIC (0x01U << CACHE_CCR_STATISTIC_Pos) ///< Statistics enable
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////////////////////////////////////////////////////////////////////////////////
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/// @brief CACHE_SR Register Bit Definition
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////////////////////////////////////////////////////////////////////////////////
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#define CACHE_SR_CS_Pos (0)
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#define CACHE_SR_CS0 (0x00U << CACHE_CCR_CS_Pos) ///< Cache is disabled
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#define CACHE_SR_CS1 (0x01U << CACHE_CCR_CS_Pos) ///< Cache is being enabled
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#define CACHE_SR_CS2 (0x02U << CACHE_CCR_CS_Pos) ///< Cache is enabled
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#define CACHE_SR_CS3 (0x03U << CACHE_CCR_CS_Pos) ///< Cache is being disabled
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#define CACHE_SR_INV_Pos (2)
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#define CACHE_SR_INV (0x01U << CACHE_CCR_INV_REQ_Pos) ///< Invalidation status
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#define CACHE_SR_POW_Pos (4)
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#define CACHE_SR_POW (0x01U << CACHE_CCR_POW_REQ_Pos) ///< SRAM power response
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////////////////////////////////////////////////////////////////////////////////
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/// @brief CACHE_IMR Register Bit Definition
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////////////////////////////////////////////////////////////////////////////////
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#define CACHE_IMR_MAN_INV_Pos (0)
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#define CACHE_IMR_MAN_INV (0x01U << CACHE_IMR_MAN_INV_Pos) ///< Mask the interrupt request of manual invalidation error
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#define CACHE_IMR_POW_Pos (1)
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#define CACHE_IMR_POW (0x01U << CACHE_IMR_POW_Pos) ///< Mask the interrupt request of power supply error
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////////////////////////////////////////////////////////////////////////////////
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/// @brief CACHE_ISR Register Bit Definition
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////////////////////////////////////////////////////////////////////////////////
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#define CACHE_ISR_MAN_INV_Pos (0)
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#define CACHE_ISR_MAN_INV (0x01U << CACHE_ISR_MAN_INV_Pos) ///< Manual invalidation of error flags
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#define CACHE_ISR_POW_Pos (1)
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#define CACHE_ISR_POW (0x01U << CACHE_ISR_POW_Pos) ///< SRAM power error flags
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////////////////////////////////////////////////////////////////////////////////
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/// @brief CACHE_CSHR Register Bit Definition
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////////////////////////////////////////////////////////////////////////////////
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#define CACHE_CSHR (0xFFFFU ) ///< Cache Hits
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////////////////////////////////////////////////////////////////////////////////
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/// @brief CACHE_CSHR Register Bit Definition
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////////////////////////////////////////////////////////////////////////////////
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#define CACHE_CSMR (0xFFFFU ) ///< Cache Lost times
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/// @}
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/// @}
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/// @}
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////////////////////////////////////////////////////////////////////////////////
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#endif
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////////////////////////////////////////////////////////////////////////////////
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