2023-07-30 20:36:47 +08:00
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/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2023-07-27 Chushicheng the first version
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*/
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#include "drv_spi.h"
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#include "pico/binary_info.h"
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#include "hardware/gpio.h"
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#include "hardware/spi.h"
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#include "hardware/dma.h"
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#ifdef BSP_USING_SPI
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#define DBG_TAG "drv.spi"
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#define DBG_LVL DBG_INFO
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#include <rtdbg.h>
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struct pico_spi
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{
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struct rt_spi_bus parent;
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spi_inst_t *handle;
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rt_uint8_t spi_rx_pin;
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rt_uint8_t spi_tx_pin;
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rt_uint8_t spi_sck_pin;
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rt_uint8_t spi_cs_pin;
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rt_uint8_t dma_tx;
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rt_uint8_t dma_rx;
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char *device_name;
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};
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static struct pico_spi pico_spi_obj[] =
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{
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#ifdef BSP_USING_SPI0
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{
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.handle = spi0,
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2024-04-01 01:59:48 +08:00
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.spi_rx_pin = BSP_SPI0_MISO_PIN,
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.spi_tx_pin = BSP_SPI0_MOSI_PIN,
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2023-11-05 16:38:44 +08:00
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.spi_sck_pin = BSP_SPI0_SCK_PIN,
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.spi_cs_pin = BSP_SPI0_CS_PIN,
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2023-07-30 20:36:47 +08:00
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.device_name = "spi0",
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},
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#endif
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#ifdef BSP_USING_SPI1
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{
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.handle = spi1,
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2024-04-01 01:59:48 +08:00
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.spi_rx_pin = BSP_SPI1_MISO_PIN,
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.spi_tx_pin = BSP_SPI1_MOSI_PIN,
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2023-11-05 16:38:44 +08:00
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.spi_sck_pin = BSP_SPI1_SCK_PIN,
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.spi_cs_pin = BSP_SPI1_CS_PIN,
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2023-07-30 20:36:47 +08:00
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.device_name = "spi1",
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},
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#endif
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};
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static rt_err_t pico_spi_init(struct pico_spi *spi_drv, struct rt_spi_configuration *cfg)
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{
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RT_ASSERT(spi_drv != RT_NULL);
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RT_ASSERT(cfg != RT_NULL);
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spi_inst_t *spi_handle = spi_drv->handle;
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spi_cpol_t cpol;
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spi_cpha_t cpha;
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rt_uint8_t dma_transfer_size;
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if (cfg->mode & RT_SPI_SLAVE)
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{
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spi_set_slave(spi_handle, true);
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}
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else
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{
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spi_set_slave(spi_handle, false);
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}
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if (cfg->mode & RT_SPI_CPHA)
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{
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cpha = SPI_CPHA_1;
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}
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else
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{
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cpha = SPI_CPHA_0;
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}
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if (cfg->mode & RT_SPI_CPOL)
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{
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cpol = SPI_CPOL_1;
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}
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else
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{
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cpol = SPI_CPOL_0;
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}
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if (cfg->data_width >= 4
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&& cfg->data_width <= 16)
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{
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spi_set_format(spi_handle, cfg->data_width, cpol, cpha, SPI_MSB_FIRST);
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}
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else
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{
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return -RT_EIO;
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}
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LOG_D("spi baudrate:%d", cfg->max_hz);
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spi_init(spi_handle, cfg->max_hz);
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gpio_set_function(spi_drv->spi_rx_pin, GPIO_FUNC_SPI);
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gpio_init(spi_drv->spi_cs_pin);
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gpio_set_function(spi_drv->spi_sck_pin, GPIO_FUNC_SPI);
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gpio_set_function(spi_drv->spi_tx_pin, GPIO_FUNC_SPI);
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// Make the SPI pins available to picotool
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bi_decl(bi_3pins_with_func(spi_drv->spi_rx_pin, spi_drv->spi_tx_pin, spi_drv->spi_sck_pin, GPIO_FUNC_SPI));
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// Make the CS pin available to picotool
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bi_decl(bi_1pin_with_name(spi_drv->spi_cs_pin, "SPI CS"));
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// Grab some unused dma channels
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spi_drv->dma_tx = dma_claim_unused_channel(true);
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spi_drv->dma_rx = dma_claim_unused_channel(true);
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/* DMA configuration */
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if(cfg->data_width == 8)
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{
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dma_transfer_size = DMA_SIZE_8;
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}
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else if(cfg->data_width == 16)
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{
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dma_transfer_size = DMA_SIZE_16;
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}
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else if(cfg->data_width == 32)
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{
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dma_transfer_size = DMA_SIZE_32;
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}
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dma_channel_config c = dma_channel_get_default_config(spi_drv->dma_tx);
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channel_config_set_transfer_data_size(&c, dma_transfer_size);
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channel_config_set_dreq(&c, spi_get_index(spi_handle) ? DREQ_SPI1_TX : DREQ_SPI0_TX);
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dma_channel_set_config(spi_drv->dma_tx, &c, false);
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c = dma_channel_get_default_config(spi_drv->dma_rx);
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channel_config_set_transfer_data_size(&c, dma_transfer_size);
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channel_config_set_dreq(&c, spi_get_index(spi_handle) ? DREQ_SPI1_RX : DREQ_SPI0_RX);
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channel_config_set_read_increment(&c, false);
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channel_config_set_write_increment(&c, true);
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dma_channel_set_config(spi_drv->dma_rx, &c, false);
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return RT_EOK;
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}
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rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, rt_base_t cs_pin)
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{
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rt_err_t ret = RT_EOK;
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struct rt_spi_device *spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device));
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ret = rt_spi_bus_attach_device_cspin(spi_device, device_name, bus_name, cs_pin, RT_NULL);
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return ret;
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}
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static rt_ssize_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message)
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{
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int i;
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RT_ASSERT(device != RT_NULL);
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RT_ASSERT(device->bus != RT_NULL);
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struct pico_spi *spi = rt_container_of(device->bus, struct pico_spi, parent);
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if(message->cs_take && (device->cs_pin != PIN_NONE))
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{
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rt_pin_write(device->cs_pin, PIN_LOW);
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}
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dma_channel_config c = dma_get_channel_config(spi->dma_tx);
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dma_channel_configure(spi->dma_tx, &c,
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&spi_get_hw(spi->handle)->dr, // write address
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(uint8_t *)(message->send_buf), // read address
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message->length, // element count (each element is of size transfer_data_size)
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false); // don't start yet
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c = dma_get_channel_config(spi->dma_rx);
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dma_channel_configure(spi->dma_rx, &c,
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(uint8_t *)(message->recv_buf), // write address
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&spi_get_hw(spi->handle)->dr, // read address
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message->length, // element count (each element is of size transfer_data_size)
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false); // don't start yet
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dma_start_channel_mask((1u << spi->dma_tx) | (1u << spi->dma_rx));
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dma_channel_wait_for_finish_blocking(spi->dma_tx);
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dma_channel_wait_for_finish_blocking(spi->dma_rx);
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if(message->cs_release && (device->cs_pin != PIN_NONE))
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{
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rt_pin_write(device->cs_pin, PIN_HIGH);
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}
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return message->length;
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}
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static rt_err_t spi_configure(struct rt_spi_device *device,
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struct rt_spi_configuration *configuration)
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{
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rt_err_t ret = RT_EOK;
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struct pico_spi *spi = rt_container_of(device->bus, struct pico_spi, parent);
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ret = pico_spi_init(spi, configuration);
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return ret;
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}
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static const struct rt_spi_ops pico_spi_ops =
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{
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.configure = spi_configure,
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.xfer = spixfer,
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};
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int rt_hw_spi_init(void)
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{
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int result = RT_EOK;
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for (rt_size_t i = 0; i < sizeof(pico_spi_obj) / sizeof(struct pico_spi); i++)
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{
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LOG_D("%s initing", pico_spi_obj[i].device_name);
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/* register spi device */
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if (rt_spi_bus_register(&pico_spi_obj[i].parent, pico_spi_obj[i].device_name, &pico_spi_ops) == RT_EOK)
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{
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LOG_D("%s init success", pico_spi_obj[i].device_name);
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}
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else
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{
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LOG_E("%s register failed", pico_spi_obj[i].device_name);
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result = -RT_ERROR;
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}
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}
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return result;
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}
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INIT_BOARD_EXPORT(rt_hw_spi_init);
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#endif /* BSP_USING_SPI */
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