489 lines
13 KiB
C
489 lines
13 KiB
C
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/*
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* Copyright (C) 2021, lizhengyang
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-09-2 lizhengyang first version
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*/
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#include <rtthread.h>
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#include "rthw.h"
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#ifdef RT_USING_PIN
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#include "drv_gpio.h"
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#include "drv_irq.h"
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#define GPIO_PCR_INTE (0x1000U)
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#define PIN_EXINT_OFF (0U)
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#define PIN_EXINT_ON (GPIO_PCR_INTE)
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#define GPIO_PIN_INDEX(pin) ((en_pin_t)((pin) & 0x0F))
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#define GPIO_PORT(pin) ((en_port_t)(((pin) >> 4) & 0x0F))
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#define GPIO_PIN(pin) ((en_pin_t)(0x01U << GPIO_PIN_INDEX(pin)))
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#define PIN_NUM(port, pin) (((((port) & 0x0F) << 4) | ((pin) & 0x0F)))
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#define PIN_MAX_NUM ((PortH * 16) + (__CLZ(__RBIT(Pin13))) + 1)
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#define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
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static void exint0_irq_handler(void);
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static void exint1_irq_handler(void);
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static void exint2_irq_handler(void);
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static void exint3_irq_handler(void);
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static void exint4_irq_handler(void);
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static void exint5_irq_handler(void);
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static void exint6_irq_handler(void);
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static void exint7_irq_handler(void);
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static void exint8_irq_handler(void);
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static void exint9_irq_handler(void);
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static void exint10_irq_handler(void);
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static void exint11_irq_handler(void);
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static void exint12_irq_handler(void);
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static void exint13_irq_handler(void);
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static void exint14_irq_handler(void);
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static void exint15_irq_handler(void);
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struct hc32_pin_irq_map
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{
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rt_uint16_t pinbit;
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struct hc32_irq_config irq_config;
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func_ptr_t irq_callback;
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};
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#ifndef HC32_PIN_CONFIG
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#define HC32_PIN_CONFIG(pin, irq, src, irq_info) \
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{ \
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.pinbit = pin, \
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.irq_callback = irq, \
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.irq_config = irq_info, \
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.irq_config.int_src = src, \
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}
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#endif /* HC32_PIN_CONFIG */
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static struct hc32_pin_irq_map pin_irq_map[] =
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{
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HC32_PIN_CONFIG(Pin00, exint0_irq_handler, INT_PORT_EIRQ0, EXINT0_IRQ_CONFIG),
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HC32_PIN_CONFIG(Pin01, exint1_irq_handler, INT_PORT_EIRQ1, EXINT1_IRQ_CONFIG),
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HC32_PIN_CONFIG(Pin02, exint2_irq_handler, INT_PORT_EIRQ2, EXINT2_IRQ_CONFIG),
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HC32_PIN_CONFIG(Pin03, exint3_irq_handler, INT_PORT_EIRQ3, EXINT3_IRQ_CONFIG),
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HC32_PIN_CONFIG(Pin04, exint4_irq_handler, INT_PORT_EIRQ4, EXINT4_IRQ_CONFIG),
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HC32_PIN_CONFIG(Pin05, exint5_irq_handler, INT_PORT_EIRQ5, EXINT5_IRQ_CONFIG),
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HC32_PIN_CONFIG(Pin06, exint6_irq_handler, INT_PORT_EIRQ6, EXINT6_IRQ_CONFIG),
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HC32_PIN_CONFIG(Pin07, exint7_irq_handler, INT_PORT_EIRQ7, EXINT7_IRQ_CONFIG),
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HC32_PIN_CONFIG(Pin08, exint8_irq_handler, INT_PORT_EIRQ8, EXINT8_IRQ_CONFIG),
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HC32_PIN_CONFIG(Pin09, exint9_irq_handler, INT_PORT_EIRQ9, EXINT9_IRQ_CONFIG),
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HC32_PIN_CONFIG(Pin10, exint10_irq_handler, INT_PORT_EIRQ10, EXINT10_IRQ_CONFIG),
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HC32_PIN_CONFIG(Pin11, exint11_irq_handler, INT_PORT_EIRQ11, EXINT11_IRQ_CONFIG),
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HC32_PIN_CONFIG(Pin12, exint12_irq_handler, INT_PORT_EIRQ12, EXINT12_IRQ_CONFIG),
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HC32_PIN_CONFIG(Pin13, exint13_irq_handler, INT_PORT_EIRQ13, EXINT13_IRQ_CONFIG),
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HC32_PIN_CONFIG(Pin14, exint14_irq_handler, INT_PORT_EIRQ14, EXINT14_IRQ_CONFIG),
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HC32_PIN_CONFIG(Pin15, exint15_irq_handler, INT_PORT_EIRQ15, EXINT15_IRQ_CONFIG),
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};
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struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
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{
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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};
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static void pin_irq_handler(rt_uint16_t pinbit)
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{
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rt_int32_t irqindex = -1;
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if (Set == EXINT_GetExIntSrc(pinbit))
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{
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EXINT_ClrExIntSrc(pinbit);
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irqindex = __CLZ(__RBIT(pinbit));
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if (pin_irq_hdr_tab[irqindex].hdr)
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{
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pin_irq_hdr_tab[irqindex].hdr(pin_irq_hdr_tab[irqindex].args);
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}
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}
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}
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static void exint0_irq_handler(void)
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{
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rt_interrupt_enter();
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pin_irq_handler(pin_irq_map[0].pinbit);
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rt_interrupt_leave();
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}
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static void exint1_irq_handler(void)
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{
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rt_interrupt_enter();
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pin_irq_handler(pin_irq_map[1].pinbit);
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rt_interrupt_leave();
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}
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static void exint2_irq_handler(void)
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{
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rt_interrupt_enter();
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pin_irq_handler(pin_irq_map[2].pinbit);
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rt_interrupt_leave();
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}
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static void exint3_irq_handler(void)
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{
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rt_interrupt_enter();
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pin_irq_handler(pin_irq_map[3].pinbit);
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rt_interrupt_leave();
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}
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static void exint4_irq_handler(void)
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{
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rt_interrupt_enter();
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pin_irq_handler(pin_irq_map[4].pinbit);
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rt_interrupt_leave();
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}
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static void exint5_irq_handler(void)
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{
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rt_interrupt_enter();
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pin_irq_handler(pin_irq_map[5].pinbit);
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rt_interrupt_leave();
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}
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static void exint6_irq_handler(void)
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{
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rt_interrupt_enter();
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pin_irq_handler(pin_irq_map[6].pinbit);
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rt_interrupt_leave();
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}
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static void exint7_irq_handler(void)
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{
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rt_interrupt_enter();
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pin_irq_handler(pin_irq_map[7].pinbit);
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rt_interrupt_leave();
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}
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static void exint8_irq_handler(void)
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{
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rt_interrupt_enter();
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pin_irq_handler(pin_irq_map[8].pinbit);
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rt_interrupt_leave();
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}
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static void exint9_irq_handler(void)
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{
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rt_interrupt_enter();
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pin_irq_handler(pin_irq_map[9].pinbit);
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rt_interrupt_leave();
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}
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static void exint10_irq_handler(void)
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{
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rt_interrupt_enter();
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pin_irq_handler(pin_irq_map[10].pinbit);
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rt_interrupt_leave();
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}
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static void exint11_irq_handler(void)
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{
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rt_interrupt_enter();
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pin_irq_handler(pin_irq_map[11].pinbit);
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rt_interrupt_leave();
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}
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static void exint12_irq_handler(void)
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{
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rt_interrupt_enter();
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pin_irq_handler(pin_irq_map[12].pinbit);
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rt_interrupt_leave();
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}
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static void exint13_irq_handler(void)
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{
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rt_interrupt_enter();
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pin_irq_handler(pin_irq_map[13].pinbit);
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rt_interrupt_leave();
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}
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static void exint14_irq_handler(void)
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{
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rt_interrupt_enter();
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pin_irq_handler(pin_irq_map[14].pinbit);
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rt_interrupt_leave();
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}
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static void exint15_irq_handler(void)
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{
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rt_interrupt_enter();
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pin_irq_handler(pin_irq_map[15].pinbit);
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rt_interrupt_leave();
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}
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static void hc32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
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{
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en_port_t gpio_port;
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en_pin_t gpio_pin;
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if (pin < PIN_MAX_NUM)
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{
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gpio_port = GPIO_PORT(pin);
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gpio_pin = GPIO_PIN(pin);
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if (PIN_LOW == value)
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{
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PORT_ResetBits(gpio_port, gpio_pin);
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}
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else
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{
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PORT_SetBits(gpio_port, gpio_pin);
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}
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}
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}
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static int hc32_pin_read(rt_device_t dev, rt_base_t pin)
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{
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en_port_t gpio_port;
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en_pin_t gpio_pin;
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int value = PIN_LOW;
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if (pin < PIN_MAX_NUM)
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{
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gpio_port = GPIO_PORT(pin);
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gpio_pin = GPIO_PIN(pin);
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if (Reset == PORT_GetBit(gpio_port, gpio_pin))
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{
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value = PIN_LOW;
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}
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else
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{
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value = PIN_HIGH;
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}
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}
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return value;
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}
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static void hc32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
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{
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en_port_t gpio_port;
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en_pin_t gpio_pin;
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stc_port_init_t stcGpioInit;
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if (pin >= PIN_MAX_NUM)
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{
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return;
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}
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MEM_ZERO_STRUCT(stcGpioInit);
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switch (mode)
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{
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case PIN_MODE_OUTPUT:
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stcGpioInit.enPinMode = Pin_Mode_Out;
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stcGpioInit.enPinOType = Pin_OType_Cmos;
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break;
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case PIN_MODE_INPUT:
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stcGpioInit.enPinMode = Pin_Mode_In;
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break;
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case PIN_MODE_INPUT_PULLUP:
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stcGpioInit.enPinMode = Pin_Mode_In;
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stcGpioInit.enPullUp = Enable;
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break;
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case PIN_MODE_INPUT_PULLDOWN:
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stcGpioInit.enPinMode = Pin_Mode_In;
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stcGpioInit.enPullUp = Disable;
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break;
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case PIN_MODE_OUTPUT_OD:
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stcGpioInit.enPinMode = Pin_Mode_Out;
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stcGpioInit.enPinOType = Pin_OType_Od;
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break;
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default:
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break;
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}
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gpio_port = GPIO_PORT(pin);
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gpio_pin = GPIO_PIN(pin);
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PORT_Init(gpio_port, gpio_pin, &stcGpioInit);
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}
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static void gpio_irq_config(uint8_t u8Port, uint16_t u16Pin, uint16_t u16ExInt)
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{
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__IO uint16_t *PCRx;
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uint16_t pin_num;
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pin_num = __CLZ(__RBIT(u16Pin));
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PCRx = (__IO uint16_t *)((uint32_t)(&M4_PORT->PCRA0) + ((uint32_t)u8Port * 0x40UL) + (pin_num * 4UL));
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PORT_Unlock();
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MODIFY_REG16(*PCRx, GPIO_PCR_INTE, u16ExInt);
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PORT_Lock();
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}
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static rt_err_t hc32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
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rt_uint32_t mode, void (*hdr)(void *args), void *args)
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{
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rt_base_t level;
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rt_int32_t irqindex = -1;
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if (pin >= PIN_MAX_NUM)
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{
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return -RT_ENOSYS;
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}
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irqindex = GPIO_PIN_INDEX(pin);
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if (irqindex >= ITEM_NUM(pin_irq_map))
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{
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return RT_ENOSYS;
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}
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level = rt_hw_interrupt_disable();
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if (pin_irq_hdr_tab[irqindex].pin == pin &&
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pin_irq_hdr_tab[irqindex].hdr == hdr &&
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pin_irq_hdr_tab[irqindex].mode == mode &&
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pin_irq_hdr_tab[irqindex].args == args)
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{
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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if (pin_irq_hdr_tab[irqindex].pin != -1)
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{
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rt_hw_interrupt_enable(level);
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return RT_EBUSY;
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}
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pin_irq_hdr_tab[irqindex].pin = pin;
|
||
|
|
pin_irq_hdr_tab[irqindex].hdr = hdr;
|
||
|
|
pin_irq_hdr_tab[irqindex].mode = mode;
|
||
|
|
pin_irq_hdr_tab[irqindex].args = args;
|
||
|
|
rt_hw_interrupt_enable(level);
|
||
|
|
|
||
|
|
return RT_EOK;
|
||
|
|
}
|
||
|
|
|
||
|
|
static rt_err_t hc32_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
|
||
|
|
{
|
||
|
|
rt_base_t level;
|
||
|
|
rt_int32_t irqindex = -1;
|
||
|
|
|
||
|
|
if (pin >= PIN_MAX_NUM)
|
||
|
|
{
|
||
|
|
return -RT_ENOSYS;
|
||
|
|
}
|
||
|
|
|
||
|
|
irqindex = GPIO_PIN_INDEX(pin);
|
||
|
|
if (irqindex >= ITEM_NUM(pin_irq_map))
|
||
|
|
{
|
||
|
|
return RT_ENOSYS;
|
||
|
|
}
|
||
|
|
|
||
|
|
level = rt_hw_interrupt_disable();
|
||
|
|
if (pin_irq_hdr_tab[irqindex].pin == -1)
|
||
|
|
{
|
||
|
|
rt_hw_interrupt_enable(level);
|
||
|
|
return RT_EOK;
|
||
|
|
}
|
||
|
|
pin_irq_hdr_tab[irqindex].pin = -1;
|
||
|
|
pin_irq_hdr_tab[irqindex].hdr = RT_NULL;
|
||
|
|
pin_irq_hdr_tab[irqindex].mode = 0;
|
||
|
|
pin_irq_hdr_tab[irqindex].args = RT_NULL;
|
||
|
|
rt_hw_interrupt_enable(level);
|
||
|
|
|
||
|
|
return RT_EOK;
|
||
|
|
}
|
||
|
|
|
||
|
|
static rt_err_t hc32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
|
||
|
|
|
||
|
|
{
|
||
|
|
struct hc32_pin_irq_map *irq_map;
|
||
|
|
rt_base_t level;
|
||
|
|
rt_int32_t irqindex = -1;
|
||
|
|
en_pin_t gpio_pin;
|
||
|
|
stc_exint_config_t stcExintInit;
|
||
|
|
|
||
|
|
if ((pin >= PIN_MAX_NUM) || ((PIN_IRQ_ENABLE != enabled) && (PIN_IRQ_DISABLE != enabled)))
|
||
|
|
{
|
||
|
|
return -RT_ENOSYS;
|
||
|
|
}
|
||
|
|
|
||
|
|
irqindex = GPIO_PIN_INDEX(pin);
|
||
|
|
if (irqindex >= ITEM_NUM(pin_irq_map))
|
||
|
|
{
|
||
|
|
return RT_ENOSYS;
|
||
|
|
}
|
||
|
|
|
||
|
|
irq_map = &pin_irq_map[irqindex];
|
||
|
|
gpio_pin = GPIO_PIN(pin);
|
||
|
|
if (enabled == PIN_IRQ_ENABLE)
|
||
|
|
{
|
||
|
|
level = rt_hw_interrupt_disable();
|
||
|
|
if (pin_irq_hdr_tab[irqindex].pin == -1)
|
||
|
|
{
|
||
|
|
rt_hw_interrupt_enable(level);
|
||
|
|
return RT_ENOSYS;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Exint config */
|
||
|
|
MEM_ZERO_STRUCT(stcExintInit);
|
||
|
|
switch (pin_irq_hdr_tab[irqindex].mode)
|
||
|
|
{
|
||
|
|
case PIN_IRQ_MODE_RISING:
|
||
|
|
stcExintInit.enExtiLvl = ExIntRisingEdge;
|
||
|
|
break;
|
||
|
|
case PIN_IRQ_MODE_FALLING:
|
||
|
|
stcExintInit.enExtiLvl = ExIntFallingEdge;
|
||
|
|
break;
|
||
|
|
case PIN_IRQ_MODE_RISING_FALLING:
|
||
|
|
stcExintInit.enExtiLvl = ExIntBothEdge;
|
||
|
|
break;
|
||
|
|
case PIN_IRQ_MODE_LOW_LEVEL:
|
||
|
|
stcExintInit.enExtiLvl = ExIntLowLevel;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
stcExintInit.enExitCh = (en_exti_ch_t)irqindex;//gpio_pin;
|
||
|
|
stcExintInit.enFilterEn = Enable;
|
||
|
|
stcExintInit.enFltClk = Pclk3Div8;
|
||
|
|
EXINT_Init(&stcExintInit);
|
||
|
|
/* IRQ sign-in */
|
||
|
|
hc32_install_irq_handler(&irq_map->irq_config, irq_map->irq_callback, RT_FALSE);
|
||
|
|
NVIC_EnableIRQ(irq_map->irq_config.irq);
|
||
|
|
gpio_irq_config(GPIO_PORT(pin), gpio_pin, PIN_EXINT_ON);
|
||
|
|
|
||
|
|
rt_hw_interrupt_enable(level);
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
level = rt_hw_interrupt_disable();
|
||
|
|
gpio_irq_config(GPIO_PORT(pin), gpio_pin, PIN_EXINT_OFF);
|
||
|
|
NVIC_DisableIRQ(irq_map->irq_config.irq);
|
||
|
|
|
||
|
|
rt_hw_interrupt_enable(level);
|
||
|
|
}
|
||
|
|
|
||
|
|
return RT_EOK;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct rt_pin_ops pin_ops =
|
||
|
|
{
|
||
|
|
hc32_pin_mode,
|
||
|
|
hc32_pin_write,
|
||
|
|
hc32_pin_read,
|
||
|
|
hc32_pin_attach_irq,
|
||
|
|
hc32_pin_detach_irq,
|
||
|
|
hc32_pin_irq_enable,
|
||
|
|
};
|
||
|
|
|
||
|
|
int rt_hw_pin_init(void)
|
||
|
|
{
|
||
|
|
return rt_device_pin_register("pin", &pin_ops, RT_NULL);
|
||
|
|
}
|
||
|
|
INIT_BOARD_EXPORT(rt_hw_pin_init);
|
||
|
|
|
||
|
|
#endif /* RT_USING_PIN */
|
||
|
|
#include "drv_gpio.h"
|
||
|
|
|