2021-08-23 10:13:53 +08:00
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/*
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2022-03-26 15:40:33 +08:00
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* Copyright (c) 2006-2022, RT-Thread Development Team
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2021-08-23 10:13:53 +08:00
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-08-23 AisinoChip the first version
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*/
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#include <rthw.h>
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#include <rtthread.h>
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#include <rtdevice.h>
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#include "rtconfig.h"
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#include "board.h"
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#include "uart_config.h"
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#ifdef RT_USING_SERIAL
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#ifdef RT_SERIAL_USING_DMA
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struct dma_config
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{
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DMA_Channel_TypeDef *Instance;
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rt_uint32_t dma_rcc;
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IRQn_Type dma_irq;
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rt_uint32_t channel;
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rt_uint32_t request;
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};
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#endif
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#ifdef RT_SERIAL_USING_DMA
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static void DMA_Configuration(struct rt_serial_device *serial, rt_uint32_t flag);
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#endif /* RT_SERIAL_USING_DMA */
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struct acm32_uart_config
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{
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const char *name;
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UART_TypeDef *Instance;
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IRQn_Type irq_type;
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enum_Enable_ID_t enable_id;
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#ifdef RT_SERIAL_USING_DMA
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struct dma_config *dma_rx;
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struct dma_config *dma_tx;
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#endif
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enum_GPIOx_t tx_port;
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enum_GPIOx_t rx_port;
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rt_uint32_t tx_pin;
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rt_uint32_t rx_pin;
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};
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struct acm32_uart
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{
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UART_HandleTypeDef handle;
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struct acm32_uart_config *config;
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#ifdef RT_SERIAL_USING_DMA
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struct
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{
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DMA_HandleTypeDef handle;
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rt_size_t last_index;
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} dma_rx;
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struct
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{
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DMA_HandleTypeDef handle;
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} dma_tx;
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#endif
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rt_uint16_t uart_dma_flag;
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struct rt_serial_device serial;
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};
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static rt_err_t uart_rx_indicate_cb(rt_device_t dev, rt_size_t size)
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{
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return RT_EOK;
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}
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static rt_err_t _uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
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{
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struct acm32_uart *uart;
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RT_ASSERT(serial != RT_NULL);
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RT_ASSERT(cfg != RT_NULL);
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uart = rt_container_of(serial, struct acm32_uart, serial);
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uart->handle.Instance = uart->config->Instance;
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uart->handle.Init.BaudRate = cfg->baud_rate;
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if (cfg->data_bits == DATA_BITS_8)
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{
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uart->handle.Init.WordLength = UART_WORDLENGTH_8B;
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}
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else /* not support */
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{
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return -RT_EINVAL;
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}
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if (cfg->stop_bits == STOP_BITS_1)
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{
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uart->handle.Init.StopBits = UART_STOPBITS_1;
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}
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else if (cfg->stop_bits == STOP_BITS_2)
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{
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uart->handle.Init.StopBits = UART_STOPBITS_2;
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}
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else /* not support */
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{
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return -RT_EINVAL;
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}
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if (cfg->parity == PARITY_NONE)
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{
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uart->handle.Init.Parity = UART_PARITY_NONE;
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}
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else if (cfg->parity == PARITY_ODD)
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{
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uart->handle.Init.Parity = UART_PARITY_ODD;
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}
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else if (cfg->parity == PARITY_EVEN)
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{
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uart->handle.Init.Parity = UART_PARITY_EVEN;
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}
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else /* not support */
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{
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return -RT_EINVAL;
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}
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uart->handle.Init.Mode = UART_MODE_TX_RX;
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uart->handle.Init.HwFlowCtl = UART_HWCONTROL_NONE;
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HAL_UART_Init(&uart->handle);
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uart->handle.Instance->LCRH &= ~UART_LCRH_FEN;
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return RT_EOK;
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}
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static rt_err_t _uart_control(struct rt_serial_device *serial, int cmd, void *arg)
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{
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struct acm32_uart *uart;
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#ifdef RT_SERIAL_USING_DMA
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rt_ubase_t ctrl_arg = (rt_ubase_t)arg;
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#endif
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RT_ASSERT(serial != RT_NULL);
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uart = rt_container_of(serial, struct acm32_uart, serial);
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switch (cmd)
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{
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/* disable interrupt */
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case RT_DEVICE_CTRL_CLR_INT:
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NVIC_DisableIRQ(uart->config->irq_type);
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/* Disable RX interrupt */
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uart->handle.Instance->IE &= ~UART_IE_RXI;
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break;
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/* enable interrupt */
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case RT_DEVICE_CTRL_SET_INT:
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NVIC_EnableIRQ(uart->config->irq_type);
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/* Enable RX interrupt */
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uart->handle.Instance->IE |= UART_IE_RXI;
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break;
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#ifdef RT_SERIAL_USING_DMA
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/* UART config */
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case RT_DEVICE_CTRL_CONFIG :
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DMA_Configuration(serial, (rt_uint32_t)ctrl_arg);
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rt_device_set_rx_indicate((rt_device_t)serial, uart_rx_indicate_cb);
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break;
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#endif /* RT_SERIAL_USING_DMA */
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}
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return RT_EOK;
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}
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static int _uart_putc(struct rt_serial_device *serial, char c)
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{
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struct acm32_uart *uart;
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RT_ASSERT(serial != RT_NULL);
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uart = rt_container_of(serial, struct acm32_uart, serial);
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while (uart->handle.Instance->FR & UART_FR_TXFF); /* wait Tx FIFO not full */
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uart->handle.Instance->DR = c;
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while ((uart->handle.Instance->FR & UART_FR_BUSY)); /* wait TX Complete */
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return 1;
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}
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static int _uart_getc(struct rt_serial_device *serial)
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{
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struct acm32_uart *uart;
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int ch;
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RT_ASSERT(serial != RT_NULL);
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uart = rt_container_of(serial, struct acm32_uart, serial);
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ch = -1;
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if (!(uart->handle.Instance->FR & UART_FR_RXFE)) /* Rx FIFO not empty */
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{
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ch = uart->handle.Instance->DR & 0xff;
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}
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return ch;
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}
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#ifdef RT_SERIAL_USING_DMA
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/**
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* Serial port receive idle process. This need add to uart idle ISR.
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*
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* @param serial serial device
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*/
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static void dma_uart_rx_idle_isr(struct rt_serial_device *serial)
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{
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struct acm32_uart *uart;
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RT_ASSERT(serial != RT_NULL);
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uart = rt_container_of(serial, struct acm32_uart, serial);
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rt_size_t recv_total_index, recv_len;
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rt_base_t level;
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/* disable interrupt */
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level = rt_hw_interrupt_disable();
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recv_total_index = uart->handle.lu32_RxSize - (uart->handle.HDMA_Rx->Instance->CTRL & 0xFFF);
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recv_len = recv_total_index - uart->handle.lu32_RxCount;
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uart->handle.lu32_RxCount = recv_total_index;
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/* enable interrupt */
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rt_hw_interrupt_enable(level);
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if (recv_len)
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{
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rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
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}
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}
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/*
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DMA receive done process. This need add to DMA receive done ISR.
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@param serial serial device
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*/
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static void dma_rx_done_isr(struct rt_serial_device *serial)
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{
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struct acm32_uart *uart;
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struct rt_serial_rx_fifo *rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx;
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RT_ASSERT(serial != RT_NULL);
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uart = rt_container_of(serial, struct acm32_uart, serial);
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rt_size_t recv_len;
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rt_base_t level;
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/* disable interrupt */
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level = rt_hw_interrupt_disable();
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recv_len = serial->config.bufsz - (uart->handle.HDMA_Rx->Instance->CTRL & 0xFFF);
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uart->dma_rx.last_index = 0;
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DMA->INT_TC_CLR |= 1 << (uart->config->dma_rx->channel); /* clear channel0 TC flag */
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/* enable interrupt */
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rt_hw_interrupt_enable(level);
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if (recv_len)
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{
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rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
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}
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HAL_UART_Receive_DMA(&(uart->handle), &rx_fifo->buffer[rx_fifo->put_index], serial->config.bufsz);
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}
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2023-02-06 07:35:33 +08:00
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static rt_ssize_t _uart_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction)
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2021-08-23 10:13:53 +08:00
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{
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struct acm32_uart *uart;
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RT_ASSERT(serial != RT_NULL);
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uart = rt_container_of(serial, struct acm32_uart, serial);
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if (size == 0)
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{
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return 0;
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}
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if (RT_SERIAL_DMA_TX == direction)
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{
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if (HAL_UART_Transmit_DMA(&uart->handle, buf, size) == HAL_OK)
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{
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rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DMADONE);
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return size;
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}
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else
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{
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return 0;
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}
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}
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return 0;
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}
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#endif /* RT_SERIAL_USING_DMA */
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static const struct rt_uart_ops acm32_uart_ops =
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{
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_uart_configure,
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_uart_control,
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_uart_putc,
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_uart_getc,
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#ifdef RT_SERIAL_USING_DMA
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_uart_dma_transmit,
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#endif
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};
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#ifdef RT_SERIAL_USING_DMA
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static void DMA_Configuration(struct rt_serial_device *serial, rt_uint32_t flag)
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{
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struct rt_serial_rx_fifo *rx_fifo;
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DMA_HandleTypeDef *DMA_Handle;
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struct dma_config *dma_config;
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struct acm32_uart *uart;
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RT_ASSERT(serial != RT_NULL);
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uart = rt_container_of(serial, struct acm32_uart, serial);
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if (RT_DEVICE_FLAG_DMA_RX == flag)
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{
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DMA_Handle = &uart->dma_rx.handle;
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dma_config = uart->config->dma_rx;
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}
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else if (RT_DEVICE_FLAG_DMA_TX == flag)
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{
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DMA_Handle = &uart->dma_tx.handle;
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dma_config = uart->config->dma_tx;
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}
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else
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{
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return;
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}
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DMA_Handle->Instance = dma_config->Instance;
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if (RT_DEVICE_FLAG_DMA_RX == flag)
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{
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DMA_Handle->Init.Data_Flow = DMA_DATA_FLOW_P2M;
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DMA_Handle->Init.Mode = DMA_NORMAL;
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DMA_Handle->Init.Source_Inc = DMA_SOURCE_ADDR_INCREASE_DISABLE;
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DMA_Handle->Init.Desination_Inc = DMA_DST_ADDR_INCREASE_ENABLE;
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}
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else if (RT_DEVICE_FLAG_DMA_TX == flag)
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{
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DMA_Handle->Init.Data_Flow = DMA_DATA_FLOW_M2P;
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DMA_Handle->Init.Mode = DMA_NORMAL;
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DMA_Handle->Init.Source_Inc = DMA_SOURCE_ADDR_INCREASE_ENABLE;
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DMA_Handle->Init.Desination_Inc = DMA_DST_ADDR_INCREASE_DISABLE;
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}
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DMA_Handle->Init.Request_ID = dma_config->request;
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DMA_Handle->Init.Source_Width = DMA_SRC_WIDTH_BYTE;
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DMA_Handle->Init.Desination_Width = DMA_DST_WIDTH_BYTE;
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if (HAL_DMA_Init(DMA_Handle) != HAL_OK)
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{
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RT_ASSERT(0);
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}
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if (RT_DEVICE_FLAG_DMA_RX == flag)
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{
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__HAL_LINK_DMA(uart->handle, HDMA_Rx, uart->dma_rx.handle);
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}
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else if (RT_DEVICE_FLAG_DMA_TX == flag)
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{
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__HAL_LINK_DMA(uart->handle, HDMA_Tx, uart->dma_tx.handle);
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}
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/* enable interrupt */
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if (flag == RT_DEVICE_FLAG_DMA_RX)
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{
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rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx;
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/* Start DMA transfer */
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if (HAL_UART_Receive_DMA(&(uart->handle), rx_fifo->buffer, serial->config.bufsz) != HAL_OK)
|
|
|
|
{
|
|
|
|
/* Transfer error in reception process */
|
|
|
|
RT_ASSERT(0);
|
|
|
|
}
|
|
|
|
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif /* RT_SERIAL_USING_DMA */
|
|
|
|
|
|
|
|
enum
|
|
|
|
{
|
|
|
|
#ifdef BSP_USING_UART1
|
|
|
|
UART1_INDEX,
|
|
|
|
#endif
|
|
|
|
#ifdef BSP_USING_UART2
|
|
|
|
UART2_INDEX,
|
|
|
|
#endif
|
|
|
|
#ifdef BSP_USING_UART3
|
|
|
|
UART3_INDEX,
|
|
|
|
#endif
|
|
|
|
UART_MAX_INDEX,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct acm32_uart_config uart_config[] =
|
|
|
|
{
|
|
|
|
#ifdef BSP_USING_UART1
|
|
|
|
UART1_CONFIG,
|
|
|
|
#endif
|
|
|
|
#ifdef BSP_USING_UART2
|
|
|
|
UART2_CONFIG,
|
|
|
|
#endif
|
|
|
|
#ifdef BSP_USING_UART3
|
|
|
|
UART3_CONFIG,
|
|
|
|
#endif
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct acm32_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = {0};
|
|
|
|
#ifdef RT_SERIAL_USING_DMA
|
|
|
|
static void uart_get_dma_config(void)
|
|
|
|
{
|
|
|
|
#if defined(BSP_USING_UART1)
|
|
|
|
#if defined(BSP_UART1_RX_USING_DMA)
|
|
|
|
static struct dma_config uart1_rx_dma_conf = UART1_DMA_RX_CONFIG;
|
|
|
|
uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
|
|
|
|
uart_config[UART1_INDEX].dma_rx = &uart1_rx_dma_conf;
|
|
|
|
#endif /* BSP_UART1_RX_USING_DMA */
|
|
|
|
#if defined(BSP_UART1_TX_USING_DMA)
|
|
|
|
static struct dma_config uart1_tx_dma_conf = UART1_DMA_TX_CONFIG;
|
|
|
|
uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
|
|
|
|
uart_config[UART1_INDEX].dma_tx = &uart1_tx_dma_conf;
|
|
|
|
#endif /* BSP_UART1_TX_USING_DMA */
|
|
|
|
#endif /* BSP_USING_UART1 */
|
|
|
|
|
|
|
|
#if defined(BSP_USING_UART2)
|
|
|
|
#if defined(BSP_UART2_RX_USING_DMA)
|
|
|
|
static struct dma_config uart2_rx_dma_conf = UART2_DMA_RX_CONFIG;
|
|
|
|
uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
|
|
|
|
uart_config[UART2_INDEX].dma_rx = &uart2_rx_dma_conf;
|
|
|
|
#endif /* BSP_UART2_RX_USING_DMA */
|
|
|
|
#if defined(BSP_UART2_TX_USING_DMA)
|
|
|
|
static struct dma_config uart2_tx_dma_conf = UART2_DMA_TX_CONFIG;
|
|
|
|
uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
|
|
|
|
uart_config[UART2_INDEX].dma_tx = &uart2_tx_dma_conf;
|
|
|
|
#endif /* BSP_UART2_TX_USING_DMA */
|
|
|
|
#endif /* BSP_USING_UART2 */
|
|
|
|
|
|
|
|
#if defined(BSP_USING_UART3)
|
|
|
|
#if defined(BSP_UART3_RX_USING_DMA)
|
|
|
|
static struct dma_config uart3_rx_dma_conf = UART3_DMA_RX_CONFIG;
|
|
|
|
uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
|
|
|
|
uart_config[UART3_INDEX].dma_rx = &uart3_rx_dma_conf;
|
|
|
|
#endif /* BSP_UART3_RX_USING_DMA */
|
|
|
|
#if defined(BSP_UART3_TX_USING_DMA)
|
|
|
|
static struct dma_config uart3_tx_dma_conf = UART3_DMA_TX_CONFIG;
|
|
|
|
uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
|
|
|
|
uart_config[UART3_INDEX].dma_tx = &uart3_tx_dma_conf;
|
|
|
|
#endif /* BSP_UART3_TX_USING_DMA */
|
|
|
|
#endif /* BSP_USING_UART3 */
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
rt_err_t rt_hw_uart_init(void)
|
|
|
|
{
|
|
|
|
rt_size_t obj_num = sizeof(uart_obj) / sizeof(struct acm32_uart);
|
|
|
|
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
|
|
|
|
rt_err_t rc = RT_EOK;
|
|
|
|
|
|
|
|
#ifdef RT_SERIAL_USING_DMA
|
|
|
|
uart_get_dma_config();
|
|
|
|
#endif
|
|
|
|
|
|
|
|
for (int i = 0; i < obj_num; i++)
|
|
|
|
{
|
|
|
|
uart_obj[i].config = &uart_config[i];
|
|
|
|
|
|
|
|
uart_obj[i].serial.ops = &acm32_uart_ops;
|
|
|
|
uart_obj[i].serial.config = config;
|
|
|
|
|
|
|
|
/* register UART device */
|
|
|
|
rc = rt_hw_serial_register(&uart_obj[i].serial, uart_obj[i].config->name,
|
|
|
|
RT_DEVICE_FLAG_RDWR
|
|
|
|
| RT_DEVICE_FLAG_INT_RX
|
|
|
|
| RT_DEVICE_FLAG_INT_TX
|
|
|
|
| uart_obj[i].uart_dma_flag
|
|
|
|
, NULL);
|
|
|
|
RT_ASSERT(rc == RT_EOK);
|
|
|
|
}
|
|
|
|
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void uart_isr(struct rt_serial_device *serial)
|
|
|
|
{
|
|
|
|
struct acm32_uart *uart = rt_container_of(serial, struct acm32_uart, serial);
|
|
|
|
|
|
|
|
RT_ASSERT(serial != RT_NULL);
|
|
|
|
|
|
|
|
/* receive interrupt enabled */
|
|
|
|
if (uart->handle.Instance->IE & UART_IE_RXI)
|
|
|
|
{
|
|
|
|
if (uart->handle.Instance->RIS & UART_RIS_RXI)
|
|
|
|
{
|
|
|
|
rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef RT_SERIAL_USING_DMA
|
|
|
|
if (uart->handle.Instance->IE & UART_IE_RTI) /* Receive TimeOut Interrupt */
|
|
|
|
{
|
|
|
|
dma_uart_rx_idle_isr(serial);
|
|
|
|
/* Clear RTI Status */
|
|
|
|
uart->handle.Instance->ICR = UART_ICR_RTI;
|
|
|
|
}
|
|
|
|
#endif /* RT_SERIAL_USING_DMA */
|
|
|
|
|
|
|
|
if (uart->handle.Instance->IE & UART_IE_TXI && \
|
|
|
|
uart->handle.Instance->RIS & UART_RIS_TXI)
|
|
|
|
{
|
|
|
|
/* Clear TXI Status */
|
|
|
|
uart->handle.Instance->ICR = UART_ICR_TXI;
|
|
|
|
if (serial->parent.open_flag & RT_DEVICE_FLAG_INT_TX)
|
|
|
|
{
|
|
|
|
rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DONE);
|
|
|
|
}
|
|
|
|
/* Disable TX interrupt */
|
|
|
|
uart->handle.Instance->IE &= ~UART_IE_TXI;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
#if defined(BSP_USING_UART1)
|
|
|
|
void UART1_IRQHandler(void)
|
|
|
|
{
|
|
|
|
/* enter interrupt */
|
|
|
|
rt_interrupt_enter();
|
|
|
|
|
|
|
|
uart_isr(&uart_obj[UART1_INDEX].serial);
|
|
|
|
|
|
|
|
/* leave interrupt */
|
|
|
|
rt_interrupt_leave();
|
|
|
|
}
|
|
|
|
#endif /* BSP_USING_UART1 */
|
|
|
|
|
|
|
|
#if defined(BSP_USING_UART2)
|
|
|
|
void UART2_IRQHandler(void)
|
|
|
|
{
|
|
|
|
/* enter interrupt */
|
|
|
|
rt_interrupt_enter();
|
|
|
|
|
|
|
|
uart_isr(&uart_obj[UART2_INDEX].serial);
|
|
|
|
|
|
|
|
/* leave interrupt */
|
|
|
|
rt_interrupt_leave();
|
|
|
|
}
|
|
|
|
#endif /* BSP_USING_UART1 */
|
|
|
|
|
|
|
|
#if defined(BSP_USING_UART3)
|
|
|
|
void UART3_IRQHandler(void)
|
|
|
|
{
|
|
|
|
/* enter interrupt */
|
|
|
|
rt_interrupt_enter();
|
|
|
|
|
|
|
|
uart_isr(&uart_obj[UART3_INDEX].serial);
|
|
|
|
|
|
|
|
/* leave interrupt */
|
|
|
|
rt_interrupt_leave();
|
|
|
|
}
|
|
|
|
#endif /* BSP_USING_UART1 */
|
|
|
|
|
|
|
|
#ifdef RT_SERIAL_USING_DMA
|
|
|
|
void DMA_IRQHandler(void)
|
|
|
|
{
|
|
|
|
/* enter interrupt */
|
|
|
|
rt_interrupt_enter();
|
|
|
|
|
|
|
|
for (int i = 0; i < UART_MAX_INDEX; i++)
|
|
|
|
{
|
|
|
|
if (DMA->RAW_INT_TC_STATUS & (1 << uart_obj[i].config->dma_rx->channel))
|
|
|
|
{
|
|
|
|
dma_rx_done_isr(&uart_obj[i].serial);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (DMA->RAW_INT_TC_STATUS & (1 << uart_obj[i].config->dma_tx->channel))
|
|
|
|
{
|
|
|
|
DMA->INT_TC_CLR |= 1 << (uart_obj[i].config->dma_tx->channel); /* clear channel0 TC flag */
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* leave interrupt */
|
|
|
|
rt_interrupt_leave();
|
|
|
|
}
|
|
|
|
#endif /* RT_SERIAL_USING_DMA */
|
|
|
|
|
|
|
|
void HAL_UART_MspInit(UART_HandleTypeDef *huart)
|
|
|
|
{
|
|
|
|
struct acm32_uart *uart;
|
|
|
|
GPIO_InitTypeDef GPIO_Uart;
|
|
|
|
|
|
|
|
RT_ASSERT(huart != RT_NULL);
|
|
|
|
|
|
|
|
/* get uart object */
|
|
|
|
uart = rt_container_of(huart, struct acm32_uart, handle);
|
|
|
|
|
|
|
|
/* Enable Clock */
|
|
|
|
System_Module_Enable(uart->config->enable_id);
|
|
|
|
|
|
|
|
/* Initialization GPIO */
|
|
|
|
GPIO_Uart.Pin = uart->config->tx_pin;
|
|
|
|
GPIO_Uart.Mode = GPIO_MODE_AF_PP;
|
|
|
|
GPIO_Uart.Pull = GPIO_PULLUP;
|
|
|
|
GPIO_Uart.Alternate = GPIO_FUNCTION_2;
|
|
|
|
HAL_GPIO_Init(uart->config->tx_port, &GPIO_Uart);
|
|
|
|
|
|
|
|
GPIO_Uart.Pin = uart->config->rx_pin;
|
|
|
|
GPIO_Uart.Mode = GPIO_MODE_AF_PP;
|
|
|
|
GPIO_Uart.Pull = GPIO_PULLUP;
|
|
|
|
GPIO_Uart.Alternate = GPIO_FUNCTION_2;
|
|
|
|
HAL_GPIO_Init(uart->config->rx_port, &GPIO_Uart);
|
|
|
|
|
|
|
|
/* NVIC Config */
|
|
|
|
NVIC_ClearPendingIRQ(uart->config->irq_type);
|
|
|
|
NVIC_SetPriority(uart->config->irq_type, 5);
|
|
|
|
NVIC_EnableIRQ(uart->config->irq_type);
|
|
|
|
}
|
|
|
|
|
|
|
|
#endif /* RT_USING_SEARIAL */
|
|
|
|
|