2021-08-23 10:13:53 +08:00
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/*
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2022-03-26 15:40:33 +08:00
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* Copyright (c) 2006-2022, RT-Thread Development Team
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2021-08-23 10:13:53 +08:00
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-08-26 AisinoChip first version
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*/
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#include <board.h>
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#include <rtthread.h>
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#include <rtdevice.h>
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2022-03-26 15:40:33 +08:00
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#ifdef RT_USING_HWTIMER
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2021-08-23 10:13:53 +08:00
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#include "tim_config.h"
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enum
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{
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#ifdef BSP_USING_TIM1
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TIM1_INDEX,
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#endif
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#ifdef BSP_USING_TIM3
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TIM3_INDEX,
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#endif
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#ifdef BSP_USING_TIM6
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TIM6_INDEX,
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#endif
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#ifdef BSP_USING_TIM14
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TIM14_INDEX,
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#endif
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#ifdef BSP_USING_TIM15
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TIM15_INDEX,
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#endif
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#ifdef BSP_USING_TIM16
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TIM16_INDEX,
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#endif
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#ifdef BSP_USING_TIM17
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TIM17_INDEX,
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#endif
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};
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struct acm32_hwtimer
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{
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rt_hwtimer_t time_device;
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TIM_HandleTypeDef tim_handle;
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IRQn_Type tim_irqn;
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char *name;
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};
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static struct acm32_hwtimer acm32_hwtimer_obj[] =
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{
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#ifdef BSP_USING_TIM1
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TIM1_CONFIG,
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#endif
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#ifdef BSP_USING_TIM3
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TIM3_CONFIG,
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#endif
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#ifdef BSP_USING_TIM6
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TIM6_CONFIG,
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#endif
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#ifdef BSP_USING_TIM14
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TIM14_CONFIG,
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#endif
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#ifdef BSP_USING_TIM15
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TIM15_CONFIG,
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#endif
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#ifdef BSP_USING_TIM16
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TIM16_CONFIG,
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#endif
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#ifdef BSP_USING_TIM17
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TIM17_CONFIG,
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#endif
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};
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static void timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state)
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{
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rt_uint32_t timer_clock = 0;
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TIM_HandleTypeDef *tim = RT_NULL;
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RT_ASSERT(timer != RT_NULL);
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if (state)
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{
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tim = (TIM_HandleTypeDef *)timer->parent.user_data;
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/* time init */
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timer_clock = System_Get_APBClock();
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if (System_Get_SystemClock() != System_Get_APBClock()) /* if hclk/pclk != 1, then timer clk = pclk * 2 */
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{
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timer_clock = System_Get_APBClock() << 1;
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}
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tim->Init.Period = (timer->freq) - 1;
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tim->Init.Prescaler = (timer_clock / timer->freq) - 1 ;
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tim->Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
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if (timer->info->cntmode == HWTIMER_CNTMODE_UP)
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{
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tim->Init.CounterMode = TIM_COUNTERMODE_UP;
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}
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else
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{
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tim->Init.CounterMode = TIM_COUNTERMODE_DOWN;
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}
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tim->Init.RepetitionCounter = 0;
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tim->Init.ARRPreLoadEn = TIM_ARR_PRELOAD_ENABLE;
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HAL_TIMER_MSP_Init(tim);
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HAL_TIMER_Base_Init(tim);
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}
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}
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static rt_err_t timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_mode_t opmode)
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{
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TIM_HandleTypeDef *tim = RT_NULL;
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RT_ASSERT(timer != RT_NULL);
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tim = (TIM_HandleTypeDef *)timer->parent.user_data;
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/* set tim cnt */
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tim->Instance->CNT = 0;
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/* set tim arr */
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tim->Instance->ARR = t - 1;
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if (opmode == HWTIMER_MODE_ONESHOT)
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{
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/* set timer to single mode */
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SET_BIT(tim->Instance->CR1, BIT3);
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}
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else
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{
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/* set timer to period mode */
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CLEAR_BIT(tim->Instance->CR1, BIT3);
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}
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/* enable IRQ */
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HAL_TIM_ENABLE_IT(tim, TIMER_INT_EN_UPD);
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/* start timer */
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HAL_TIMER_Base_Start(tim->Instance);
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return RT_EOK;
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}
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static void timer_stop(rt_hwtimer_t *timer)
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{
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TIM_HandleTypeDef *tim = RT_NULL;
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RT_ASSERT(timer != RT_NULL);
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tim = (TIM_HandleTypeDef *)timer->parent.user_data;
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/* stop timer */
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HAL_TIMER_Base_Stop(tim->Instance);
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}
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static rt_err_t timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg)
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{
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TIM_HandleTypeDef *tim = RT_NULL;
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rt_err_t result = RT_EOK;
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RT_ASSERT(timer != RT_NULL);
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RT_ASSERT(arg != RT_NULL);
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tim = (TIM_HandleTypeDef *)timer->parent.user_data;
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switch (cmd)
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{
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case HWTIMER_CTRL_FREQ_SET:
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{
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rt_uint32_t freq;
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rt_uint32_t timer_clock;
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rt_uint16_t val;
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/* set timer frequence */
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freq = *((rt_uint32_t *)arg);
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timer_clock = System_Get_APBClock();
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if (System_Get_SystemClock() != System_Get_APBClock()) /* if hclk/pclk != 1, then timer clk = pclk * 2 */
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{
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timer_clock = System_Get_APBClock() << 1;
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}
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val = timer_clock / freq;
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tim->Instance->PSC = val - 1;
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/* Update frequency value */
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tim->Instance->CR1 = BIT2; /* CEN=0, URS=1, OPM = 0 */
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tim->Instance->EGR |= TIM_EVENTSOURCE_UPDATE;
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}
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break;
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default:
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{
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result = -RT_ENOSYS;
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}
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break;
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}
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return result;
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}
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static rt_uint32_t timer_counter_get(rt_hwtimer_t *timer)
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{
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RT_ASSERT(timer != RT_NULL);
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return ((TIM_HandleTypeDef *)timer->parent.user_data)->Instance->CNT;
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}
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static const struct rt_hwtimer_info _info = TIM_DEV_INFO_CONFIG;
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static const struct rt_hwtimer_ops _ops =
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{
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.init = timer_init,
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.start = timer_start,
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.stop = timer_stop,
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.count_get = timer_counter_get,
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.control = timer_ctrl,
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};
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#ifdef BSP_USING_TIM1
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void TIM1_BRK_UP_TRG_COM_IRQHandler(void)
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{
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/* enter interrupt */
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rt_interrupt_enter();
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/* interrupt service routine */
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if (TIM1->SR & TIMER_SR_UIF)
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{
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rt_device_hwtimer_isr(&acm32_hwtimer_obj[TIM1_INDEX].time_device);
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}
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TIM1->SR = 0; /* write 0 to clear hardware flag */
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/* leave interrupt */
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rt_interrupt_leave();
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}
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#endif
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#ifdef BSP_USING_TIM3
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void TIM3_IRQHandler(void)
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{
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/* enter interrupt */
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rt_interrupt_enter();
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if (TIM3->SR & TIMER_SR_UIF)
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{
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rt_device_hwtimer_isr(&acm32_hwtimer_obj[TIM3_INDEX].time_device);
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}
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TIM3->SR = 0; /* write 0 to clear hardware flag */
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/* leave interrupt */
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rt_interrupt_leave();
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}
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#endif
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#ifdef BSP_USING_TIM6
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void TIM6_IRQHandler(void)
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{
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/* enter interrupt */
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rt_interrupt_enter();
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/* interrupt service routine */
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if (TIM6->SR & TIMER_SR_UIF)
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{
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rt_device_hwtimer_isr(&acm32_hwtimer_obj[TIM6_INDEX].time_device);
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}
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TIM6->SR = 0; /* write 0 to clear hardware flag */
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/* leave interrupt */
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rt_interrupt_leave();
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}
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#endif
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#ifdef BSP_USING_TIM14
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void TIM14_IRQHandler(void)
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{
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/* enter interrupt */
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rt_interrupt_enter();
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/* interrupt service routine */
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if (TIM14->SR & TIMER_SR_UIF)
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{
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rt_device_hwtimer_isr(&acm32_hwtimer_obj[TIM14_INDEX].time_device);
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}
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TIM14->SR = 0; /* write 0 to clear hardware flag */
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/* leave interrupt */
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rt_interrupt_leave();
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}
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#endif
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#ifdef BSP_USING_TIM15
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void TIM15_IRQHandler(void)
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{
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/* enter interrupt */
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rt_interrupt_enter();
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/* interrupt service routine */
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if (TIM15->SR & TIMER_SR_UIF)
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{
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rt_device_hwtimer_isr(&acm32_hwtimer_obj[TIM15_INDEX].time_device);
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}
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TIM15->SR = 0; /* write 0 to clear hardware flag */
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/* leave interrupt */
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rt_interrupt_leave();
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}
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#endif
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#ifdef BSP_USING_TIM16
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void TIM16_IRQHandler(void)
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{
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/* enter interrupt */
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rt_interrupt_enter();
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if (TIM16->SR & TIMER_SR_UIF)
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{
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rt_device_hwtimer_isr(&acm32_hwtimer_obj[TIM16_INDEX].time_device);
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}
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TIM16->SR = 0; /* write 0 to clear hardware flag */
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/* leave interrupt */
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rt_interrupt_leave();
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}
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#endif
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#ifdef BSP_USING_TIM17
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void TIM17_IRQHandler(void)
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{
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/* enter interrupt */
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rt_interrupt_enter();
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if (TIM17->SR & TIMER_SR_UIF)
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{
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rt_device_hwtimer_isr(&acm32_hwtimer_obj[TIM17_INDEX].time_device);
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}
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TIM17->SR = 0; /* write 0 to clear hardware flag */
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/* leave interrupt */
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rt_interrupt_leave();
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}
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#endif
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static int acm32_hwtimer_init(void)
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{
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int i = 0;
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int result = RT_EOK;
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for (i = 0; i < sizeof(acm32_hwtimer_obj) / sizeof(acm32_hwtimer_obj[0]); i++)
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{
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acm32_hwtimer_obj[i].time_device.info = &_info;
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acm32_hwtimer_obj[i].time_device.ops = &_ops;
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result = rt_device_hwtimer_register(&acm32_hwtimer_obj[i].time_device,
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acm32_hwtimer_obj[i].name,
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&acm32_hwtimer_obj[i].tim_handle);
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if (result != RT_EOK)
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{
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result = -RT_ERROR;
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break;
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}
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}
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return result;
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}
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INIT_BOARD_EXPORT(acm32_hwtimer_init);
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#endif /* RT_USING_HWTIMER */
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