647 lines
18 KiB
C
647 lines
18 KiB
C
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/*
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* Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/******************************************************************************
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* @file dw_iic.c
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* @brief CSI Source File for IIC Driver
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* @version V1.0
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* @date 02. June 2017
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******************************************************************************/
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#include "csi_core.h"
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#include "drv_iic.h"
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#include "dw_iic.h"
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#include "soc.h"
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#include "string.h"
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#define ERR_IIC(errno) (CSI_DRV_ERRNO_I2C_BASE | errno)
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#define IIC_NULL_PARAM_CHK(para) \
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do { \
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if (para == NULL) { \
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return ERR_IIC(EDRV_PARAMETER); \
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} \
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} while (0)
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typedef struct {
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uint32_t base;
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uint32_t irq;
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iic_event_cb_t cb_event;
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void *cb_arg;
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uint32_t rx_total_num;
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uint32_t tx_total_num;
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void *rx_buf;
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void *tx_buf;
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volatile uint32_t rx_cnt;
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volatile uint32_t tx_cnt;
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uint32_t status; ///< status of iic transfer
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} dw_iic_priv_t;
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static dw_iic_priv_t iic_instance[CONFIG_IIC_NUM];
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static const iic_capabilities_t iic_capabilities = {
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.address_10_bit = 0 /* supports 10-bit addressing */
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};
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static inline void dw_iic_disable(dw_iic_reg_t *addr)
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{
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/* First clear ACTIVITY, then Disable IIC */
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addr->IC_CLR_ACTIVITY;
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addr->IC_ENABLE = DW_IIC_DISABLE;
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}
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static inline void dw_iic_enable(dw_iic_reg_t *addr)
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{
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addr->IC_ENABLE = DW_IIC_ENABLE;
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}
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static inline void dw_iic_set_transfer_speed(dw_iic_reg_t *addr, DWENUM_IIC_SPEED speed)
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{
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uint16_t temp = addr->IC_CON;
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temp &= ~((1 << 1) + (1 << 2));
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temp |= speed << 1;
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addr->IC_CON = temp;
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}
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static inline void dw_iic_set_target_address(dw_iic_reg_t *addr, uint16_t address)
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{
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uint16_t temp = addr->IC_TAR;
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temp &= 0xfc00;
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temp |= address;
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addr->IC_TAR = temp;
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}
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static inline void dw_iic_set_addr_mode(dw_iic_reg_t *addr, iic_address_mode_e addr_mode)
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{
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uint16_t temp = addr->IC_TAR;
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temp &= 0xefff;
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temp |= addr_mode << 12;
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addr->IC_TAR = temp;
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}
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static void dw_i2c_int_clear(dw_iic_reg_t *addr, DWENUM_IIC_INTERRUPT_TYPE type)
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{
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uint32_t temp = 0;
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switch (type) {
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case DW_IIC_RX_UNDER:
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temp = addr->IC_CLR_RX_UNDER;
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break;
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case DW_IIC_RX_OVER:
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temp = addr->IC_CLR_RX_OVER;
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break;
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case DW_IIC_TX_OVER:
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temp = addr->IC_CLR_TX_OVER;
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break;
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case DW_IIC_RD_REQ:
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temp = addr->IC_CLR_RD_REQ;
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break;
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case DW_IIC_TX_ABRT:
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temp = addr->IC_CLR_TX_ABRT;
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break;
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case DW_IIC_RX_DONE:
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temp = addr->IC_CLR_RX_DONE;
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break;
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case DW_IIC_ACTIVITY:
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temp = addr->IC_CLR_ACTIVITY;
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break;
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case DW_IIC_STOP_DET:
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temp = addr->IC_CLR_STOP_DET;
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break;
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case DW_IIC_START_DET:
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temp = addr->IC_CLR_START_DET;
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break;
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case DW_IIC_GEN_CALL:
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temp = addr->IC_CLR_GEN_CALL;
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break;
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default:
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temp = addr->IC_CLR_INTR;
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}
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}
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/**
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\brief interrupt service function for transmit FIFO empty interrupt.
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\param[in] iic_priv pointer to iic private.
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*/
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static void dw_iic_intr_tx_empty(dw_iic_priv_t *iic_priv)
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{
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dw_iic_reg_t *addr = (dw_iic_reg_t *)(iic_priv->base);
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if (addr->IC_INTR_STAT & (1 << DW_IIC_TX_EMPTY)) {
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uint32_t remain_txfifo = iic_priv->tx_total_num - iic_priv->tx_cnt;
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uint8_t emptyfifo = (remain_txfifo > (DW_IIC_FIFO_MAX_LV - addr->IC_TXFLR)) ? DW_IIC_FIFO_MAX_LV - addr->IC_TXFLR : remain_txfifo;
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uint32_t i = 0u;
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for (i = 0; i < emptyfifo; i++) {
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addr->IC_DATA_CMD = *((uint8_t *)(iic_priv->tx_buf)++);
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}
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iic_priv->tx_cnt += emptyfifo;
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if (iic_priv->tx_cnt == iic_priv->tx_total_num) {
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addr->IC_INTR_MASK &= ~(1 << DW_IIC_TX_EMPTY);
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}
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}
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if (addr->IC_INTR_STAT & (1 << DW_IIC_TX_OVER)) {
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dw_i2c_int_clear(addr, DW_IIC_TX_OVER);
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iic_priv->status = IIC_STATE_ERROR;
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dw_iic_disable(addr);
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if (iic_priv->cb_event) {
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iic_priv->cb_event(I2C_EVENT_BUS_ERROR, iic_priv->cb_arg);
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}
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}
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if (addr->IC_INTR_STAT & (1 << DW_IIC_TX_ABRT)) {
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dw_i2c_int_clear(addr, DW_IIC_TX_ABRT);
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iic_priv->status = IIC_STATE_ERROR;
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dw_iic_disable(addr);
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if (iic_priv->cb_event) {
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iic_priv->cb_event(I2C_EVENT_BUS_ERROR, iic_priv->cb_arg);
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}
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}
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if (addr->IC_INTR_STAT & (1 << DW_IIC_STOP_DET)) {
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iic_priv->status = IIC_STATE_DONE;
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dw_i2c_int_clear(addr, DW_IIC_STOP_DET);
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if (iic_priv->cb_event) {
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dw_iic_disable(addr);
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addr->IC_CLR_INTR;
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iic_priv->cb_event(I2C_EVENT_TRANSFER_DONE, iic_priv->cb_arg);
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}
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}
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}
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/**
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\brief interrupt service function for receive FIFO full interrupt .
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\param[in] iic_priv pointer to iic private.
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*/
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static void dw_iic_intr_rx_full(dw_iic_priv_t *iic_priv)
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{
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dw_iic_reg_t *addr = (dw_iic_reg_t *)(iic_priv->base);
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if (addr->IC_INTR_STAT & (1 << DW_IIC_RX_FULL)) {
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uint8_t emptyfifo = addr->IC_RXFLR;
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uint32_t i = 0u;
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for (i = 0; i < emptyfifo ; i++) {
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*((uint8_t *)(iic_priv->rx_buf++)) = ((addr->IC_DATA_CMD) & 0xff);
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}
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iic_priv->rx_cnt += emptyfifo;
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if (iic_priv->rx_cnt != iic_priv->rx_total_num) {
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addr->IC_DATA_CMD = 1 << 8;
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}
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}
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if (addr->IC_INTR_STAT & (1 << DW_IIC_RX_OVER)) {
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dw_i2c_int_clear(addr, DW_IIC_RX_OVER);
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iic_priv->status = IIC_STATE_ERROR;
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dw_iic_disable(addr);
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if (iic_priv->cb_event) {
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iic_priv->cb_event(I2C_EVENT_BUS_ERROR, iic_priv->cb_arg);
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}
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}
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if (addr->IC_INTR_STAT & (1 << DW_IIC_RX_FULL)) {
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dw_i2c_int_clear(addr, DW_IIC_RX_FULL);
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iic_priv->status = IIC_STATE_ERROR;
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dw_iic_disable(addr);
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if (iic_priv->cb_event) {
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iic_priv->cb_event(I2C_EVENT_BUS_ERROR, iic_priv->cb_arg);
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}
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}
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if (addr->IC_INTR_STAT & (1 << DW_IIC_STOP_DET)) {
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dw_i2c_int_clear(addr, DW_IIC_STOP_DET);
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if (iic_priv->rx_cnt == iic_priv->rx_total_num) {
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iic_priv->status = IIC_STATE_DONE;
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dw_iic_disable(addr);
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addr->IC_CLR_INTR;
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if (iic_priv->cb_event) {
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iic_priv->cb_event(I2C_EVENT_TRANSFER_DONE, iic_priv->cb_arg);
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}
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}
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}
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}
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void dw_iic_irqhandler(int32_t idx)
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{
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dw_iic_priv_t *iic_priv = &iic_instance[idx];
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dw_iic_reg_t *addr = (dw_iic_reg_t *)(iic_priv->base);
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if (addr->IC_INTR_STAT & (1 << DW_IIC_TX_ABRT)) {
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/* If arbitration fault, it indicates either a slave device not
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* responding as expected, or other master which is not supported
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* by this SW.
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*/
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dw_i2c_int_clear(addr, DW_IIC_TX_ABRT);
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iic_priv->status = IIC_STATE_DONE;
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if (iic_priv->cb_event) {
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dw_iic_disable(addr);
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iic_priv->cb_event(I2C_EVENT_BUS_ERROR, iic_priv->cb_arg);
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return;
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}
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}
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switch (iic_priv->status) {
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/* send data to slave */
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case IIC_STATE_DATASEND: {
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dw_iic_intr_tx_empty(iic_priv);
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break;
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}
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/* wait for data from slave */
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case IIC_STATE_WFDATA: {
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dw_iic_intr_rx_full(iic_priv);
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break;
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}
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/* unexpected state,SW fault */
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default: {
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dw_iic_disable(addr);
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if (iic_priv->cb_event) {
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iic_priv->cb_event(I2C_EVENT_BUS_ERROR, iic_priv->cb_arg);
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}
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}
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}
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}
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int32_t __attribute__((weak)) target_iic_init(pin_t scl, pin_t sda, uint32_t *base, uint32_t *irq)
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{
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return -1;
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}
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/**
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\brief Initialize IIC Interface. 1. Initializes the resources needed for the IIC interface 2.registers event callback function
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\param[in] handle iic handle to operate.
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\param[in] cb_event Pointer to \ref iic_event_cb_t
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\return error code
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*/
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iic_handle_t csi_iic_initialize(pin_t scl, pin_t sda, iic_event_cb_t cb_event, void *cb_arg)
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{
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uint32_t base = 0u;
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uint32_t irq = 0u;
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int32_t idx = target_iic_init(scl, sda, &base, &irq);
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if (idx < 0 || idx >= CONFIG_IIC_NUM) {
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return NULL;
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}
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dw_iic_priv_t *iic_priv = &iic_instance[idx];
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iic_priv->base = base;
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iic_priv->irq = irq;
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iic_priv->cb_event = cb_event;
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iic_priv->cb_arg = cb_arg;
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iic_priv->rx_total_num = 0;
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iic_priv->tx_total_num = 0;
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iic_priv->rx_buf = NULL;
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iic_priv->tx_buf = NULL;
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iic_priv->rx_cnt = 0;
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iic_priv->tx_cnt = 0;
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iic_priv->status = 0;
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dw_iic_reg_t *addr = (dw_iic_reg_t *)(iic_priv->base);
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/* mask all interrupts */
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addr->IC_INTR_MASK = 0x00;
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addr->IC_CON = DW_IIC_CON_DEFAUL;
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addr->IC_INTR_MASK |= 1 << DW_IIC_TX_ABRT;
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addr->IC_INTR_MASK |= 1 << DW_IIC_TX_OVER;
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addr->IC_INTR_MASK |= 1 << DW_IIC_RX_OVER;
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addr->IC_INTR_MASK |= 1 << DW_IIC_RX_FULL;
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addr->IC_INTR_MASK |= 1 << DW_IIC_STOP_DET;
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drv_nvic_enable_irq(iic_priv->irq);
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return iic_priv;
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}
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/**
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\brief De-initialize IIC Interface. stops operation and releases the software resources used by the interface
|
||
|
|
\param[in] handle iic handle to operate.
|
||
|
|
\return error code
|
||
|
|
*/
|
||
|
|
int32_t csi_iic_uninitialize(iic_handle_t handle)
|
||
|
|
{
|
||
|
|
IIC_NULL_PARAM_CHK(handle);
|
||
|
|
|
||
|
|
/* First clear ACTIVITY, then Disable IIC */
|
||
|
|
dw_iic_priv_t *iic_priv = handle;
|
||
|
|
dw_iic_reg_t *addr = (dw_iic_reg_t *)(iic_priv->base);
|
||
|
|
|
||
|
|
addr->IC_CLR_ACTIVITY;
|
||
|
|
addr->IC_INTR_MASK = 0x00;
|
||
|
|
addr->IC_ENABLE = DW_IIC_DISABLE;
|
||
|
|
|
||
|
|
iic_priv->cb_event = NULL;
|
||
|
|
iic_priv->rx_total_num = 0;
|
||
|
|
iic_priv->tx_total_num = 0;
|
||
|
|
iic_priv->rx_buf = NULL;
|
||
|
|
iic_priv->tx_buf = NULL;
|
||
|
|
iic_priv->rx_cnt = 0;
|
||
|
|
iic_priv->tx_cnt = 0;
|
||
|
|
iic_priv->status = 0;
|
||
|
|
|
||
|
|
drv_nvic_disable_irq(iic_priv->irq);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
\brief Get driver capabilities.
|
||
|
|
\return \ref iic_capabilities_t
|
||
|
|
*/
|
||
|
|
iic_capabilities_t csi_iic_get_capabilities(iic_handle_t handle)
|
||
|
|
{
|
||
|
|
return iic_capabilities;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
\brief config iic.
|
||
|
|
\param[in] handle iic handle to operate.
|
||
|
|
\param[in] mode \ref iic_mode_e.if negative, then this attribute not changed
|
||
|
|
\param[in] speed \ref iic_speed_e.if negative, then this attribute not changed
|
||
|
|
\param[in] addr_mode \ref iic_address_mode_e.if negative, then this attribute not changed
|
||
|
|
\param[in] slave_addr slave address.if negative, then this attribute not changed
|
||
|
|
\return error code
|
||
|
|
*/
|
||
|
|
int32_t csi_iic_config(iic_handle_t handle,
|
||
|
|
iic_mode_e mode,
|
||
|
|
iic_speed_e speed,
|
||
|
|
iic_address_mode_e addr_mode,
|
||
|
|
int32_t slave_addr)
|
||
|
|
{
|
||
|
|
IIC_NULL_PARAM_CHK(handle);
|
||
|
|
|
||
|
|
if (mode >= 0) {
|
||
|
|
switch (mode) {
|
||
|
|
case IIC_MODE_MASTER:
|
||
|
|
break;
|
||
|
|
|
||
|
|
case IIC_MODE_SLAVE:
|
||
|
|
return ERR_IIC(EDRV_UNSUPPORTED);
|
||
|
|
break;
|
||
|
|
|
||
|
|
default:
|
||
|
|
return ERR_IIC(EDRV_PARAMETER);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
dw_iic_reg_t *addr = (dw_iic_reg_t *)(((dw_iic_priv_t *)handle)->base);
|
||
|
|
|
||
|
|
if (speed >= 0) {
|
||
|
|
switch (speed) {
|
||
|
|
case I2C_BUS_SPEED_STANDARD:
|
||
|
|
dw_iic_set_transfer_speed(addr, DW_IIC_STANDARDSPEED);
|
||
|
|
break;
|
||
|
|
|
||
|
|
case I2C_BUS_SPEED_FAST:
|
||
|
|
dw_iic_set_transfer_speed(addr, DW_IIC_FASTSPEED);
|
||
|
|
break;
|
||
|
|
|
||
|
|
case I2C_BUS_SPEED_FAST_PLUS:
|
||
|
|
return ERR_IIC(EDRV_UNSUPPORTED);
|
||
|
|
|
||
|
|
case I2C_BUS_SPEED_HIGH:
|
||
|
|
dw_iic_set_transfer_speed(addr, DW_IIC_HIGHSPEED);
|
||
|
|
break;
|
||
|
|
|
||
|
|
default:
|
||
|
|
return ERR_IIC(EDRV_PARAMETER);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
if (addr_mode >= 0) {
|
||
|
|
switch (addr_mode) {
|
||
|
|
case I2C_ADDRESS_10BIT:
|
||
|
|
case I2C_ADDRESS_7BIT:
|
||
|
|
dw_iic_set_addr_mode(addr, addr_mode);
|
||
|
|
break;
|
||
|
|
|
||
|
|
default:
|
||
|
|
return ERR_IIC(EDRV_PARAMETER);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
if (slave_addr >= 0) {
|
||
|
|
dw_iic_set_target_address(addr, slave_addr);
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
\brief Start transmitting data as I2C Master.
|
||
|
|
\param[in] handle iic handle to operate.
|
||
|
|
\param[in] data Pointer to buffer with data to transmit to I2C Slave
|
||
|
|
\param[in] num Number of data items to send
|
||
|
|
\param[in] xfer_pending Transfer operation is pending - Stop condition will not be generated
|
||
|
|
\return error code
|
||
|
|
*/
|
||
|
|
int32_t csi_iic_master_send(iic_handle_t handle, const void *data, uint32_t num, bool xfer_pending)
|
||
|
|
{
|
||
|
|
IIC_NULL_PARAM_CHK(handle);
|
||
|
|
|
||
|
|
if (data == NULL || num == 0) {
|
||
|
|
return ERR_IIC(EDRV_PARAMETER);
|
||
|
|
}
|
||
|
|
|
||
|
|
dw_iic_priv_t *iic_priv = handle;
|
||
|
|
dw_iic_reg_t *addr = (dw_iic_reg_t *)(iic_priv->base);
|
||
|
|
|
||
|
|
iic_priv->tx_buf = (uint8_t *)data;
|
||
|
|
iic_priv->tx_total_num = num;
|
||
|
|
iic_priv->tx_cnt = 0;
|
||
|
|
iic_priv->status = IIC_STATE_DATASEND;
|
||
|
|
|
||
|
|
dw_iic_disable(addr);
|
||
|
|
addr->IC_CLR_INTR;
|
||
|
|
|
||
|
|
uint32_t length = (num > DW_IIC_FIFO_MAX_LV) ? DW_IIC_FIFO_MAX_LV : num;
|
||
|
|
addr->IC_TX_TL = DW_IIC_TXFIFO_LV;
|
||
|
|
|
||
|
|
dw_iic_enable(addr);
|
||
|
|
uint32_t i = 0u;
|
||
|
|
|
||
|
|
for (i = 0; i < length; i++) {
|
||
|
|
addr->IC_DATA_CMD = *((uint8_t *)(iic_priv->tx_buf)++);
|
||
|
|
}
|
||
|
|
|
||
|
|
iic_priv->tx_cnt += length;
|
||
|
|
|
||
|
|
/* open corresponding interrupts */
|
||
|
|
addr->IC_INTR_MASK |= 1 << DW_IIC_TX_EMPTY;
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
\fn int32_t csi_iic_master_receive (iic_handle_t handle,const void *data, uint32_t num, bool xfer_pending)
|
||
|
|
\brief Start receiving data as I2C Master.
|
||
|
|
\param[in] handle iic handle to operate.
|
||
|
|
\param[out] data Pointer to buffer for data to receive from IIC receiver
|
||
|
|
\param[in] num Number of data items to receive
|
||
|
|
\param[in] xfer_pending Transfer operation is pending - Stop condition will not be generated
|
||
|
|
\return error code
|
||
|
|
*/
|
||
|
|
int32_t csi_iic_master_receive(iic_handle_t handle, const void *data, uint32_t num, bool xfer_pending)
|
||
|
|
{
|
||
|
|
IIC_NULL_PARAM_CHK(handle);
|
||
|
|
|
||
|
|
if (data == NULL || num == 0) {
|
||
|
|
return ERR_IIC(EDRV_PARAMETER);
|
||
|
|
}
|
||
|
|
|
||
|
|
dw_iic_priv_t *iic_priv = handle;
|
||
|
|
|
||
|
|
iic_priv->rx_buf = (uint8_t *)data;
|
||
|
|
iic_priv->rx_total_num = num;
|
||
|
|
iic_priv->rx_cnt = 0;
|
||
|
|
iic_priv->status = IIC_STATE_WFDATA;
|
||
|
|
|
||
|
|
dw_iic_reg_t *addr = (dw_iic_reg_t *)(iic_priv->base);
|
||
|
|
dw_iic_disable(addr);
|
||
|
|
|
||
|
|
int32_t tmp = addr->IC_CLR_INTR;
|
||
|
|
addr->IC_RX_TL = DW_IIC_FIFO_MAX_LV; /* Sets receive FIFO threshold */
|
||
|
|
|
||
|
|
tmp = addr->IC_CLR_INTR;
|
||
|
|
addr->IC_RX_TL = DW_IIC_RXFIFO_LV; /* Sets receive FIFO threshold */
|
||
|
|
dw_iic_enable(addr);
|
||
|
|
addr->IC_DATA_CMD = 1 << 8;
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
\brief Start transmitting data as I2C Slave.
|
||
|
|
\param[in] handle iic handle to operate.
|
||
|
|
\param[in] data Pointer to buffer with data to transmit to I2C Master
|
||
|
|
\param[in] num Number of data items to send
|
||
|
|
\return error code
|
||
|
|
*/
|
||
|
|
int32_t csi_iic_slave_send(iic_handle_t handle, const void *data, uint32_t num)
|
||
|
|
{
|
||
|
|
return ERR_IIC(EDRV_UNSUPPORTED);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
\fn int32_t csi_iic_slave_receive (iic_handle_t handle, const void *data, uint32_t num)
|
||
|
|
\brief Start receiving data as I2C Slave.
|
||
|
|
\param[in] handle iic handle to operate.
|
||
|
|
\param[out] data Pointer to buffer for data to receive from I2C Master
|
||
|
|
\param[in] num Number of data items to receive
|
||
|
|
\return error code
|
||
|
|
*/
|
||
|
|
int32_t csi_iic_slave_receive(iic_handle_t handle, const void *data, uint32_t num)
|
||
|
|
{
|
||
|
|
return ERR_IIC(EDRV_UNSUPPORTED);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
\brief abort transfer.
|
||
|
|
\param[in] handle iic handle to operate.
|
||
|
|
\return error code
|
||
|
|
*/
|
||
|
|
int32_t csi_iic_abort_transfer(iic_handle_t handle)
|
||
|
|
{
|
||
|
|
IIC_NULL_PARAM_CHK(handle);
|
||
|
|
|
||
|
|
dw_iic_priv_t *iic_priv = handle;
|
||
|
|
dw_iic_reg_t *addr = (dw_iic_reg_t *)(iic_priv->base);
|
||
|
|
|
||
|
|
dw_iic_disable(addr);
|
||
|
|
iic_priv->rx_cnt = 0;
|
||
|
|
iic_priv->tx_cnt = 0;
|
||
|
|
iic_priv->rx_buf = NULL;
|
||
|
|
iic_priv->tx_buf = NULL;
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
/**
|
||
|
|
\brief Get IIC status.
|
||
|
|
\param[in] handle iic handle to operate.
|
||
|
|
\return IIC status \ref iic_status_t
|
||
|
|
*/
|
||
|
|
iic_status_t csi_iic_get_status(iic_handle_t handle)
|
||
|
|
{
|
||
|
|
iic_status_t iic_status = {0};
|
||
|
|
|
||
|
|
if (handle == NULL) {
|
||
|
|
return iic_status;
|
||
|
|
}
|
||
|
|
|
||
|
|
dw_iic_priv_t *iic_priv = handle;
|
||
|
|
dw_iic_reg_t *addr = (dw_iic_reg_t *)(iic_priv->base);
|
||
|
|
|
||
|
|
int32_t tmp = addr->IC_STATUS;
|
||
|
|
|
||
|
|
if (tmp & 0x1) {
|
||
|
|
iic_status.busy = 1;
|
||
|
|
|
||
|
|
if (tmp & 0x40) {
|
||
|
|
iic_status.mode = 0;
|
||
|
|
} else {
|
||
|
|
iic_status.mode = 1;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
if (iic_priv->status == IIC_STATE_WFDATA) {
|
||
|
|
iic_status.direction = 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (addr->IC_RAW_INTR_STAT & 0x800) {
|
||
|
|
iic_status.general_call = 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (iic_priv->status == IIC_STATE_ERROR) {
|
||
|
|
iic_status.bus_error = 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
return iic_status;
|
||
|
|
}
|
||
|
|
|