224 lines
12 KiB
C
224 lines
12 KiB
C
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//*****************************************************************************
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//
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// hw_onewire.h - Macros used when accessing the One wire hardware.
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//
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// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved.
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// Software License Agreement
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package.
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//
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//*****************************************************************************
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#ifndef __HW_ONEWIRE_H__
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#define __HW_ONEWIRE_H__
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//*****************************************************************************
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//
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// The following are defines for the One wire register offsets.
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//
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//*****************************************************************************
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#define ONEWIRE_O_CS 0x00000000 // 1-Wire Control and Status
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#define ONEWIRE_O_TIM 0x00000004 // 1-Wire Timing Override
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#define ONEWIRE_O_DATW 0x00000008 // 1-Wire Data Write
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#define ONEWIRE_O_DATR 0x0000000C // 1-Wire Data Read
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#define ONEWIRE_O_IM 0x00000100 // 1-Wire Interrupt Mask
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#define ONEWIRE_O_RIS 0x00000104 // 1-Wire Raw Interrupt Status
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#define ONEWIRE_O_MIS 0x00000108 // 1-Wire Masked Interrupt Status
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#define ONEWIRE_O_ICR 0x0000010C // 1-Wire Interrupt Clear
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#define ONEWIRE_O_DMA 0x00000120 // 1-Wire uDMA Control
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#define ONEWIRE_O_PP 0x00000FC0 // 1-Wire Peripheral Properties
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the ONEWIRE_O_CS register.
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//
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//*****************************************************************************
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#define ONEWIRE_CS_USEALT 0x80000000 // Two Wire Enable
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#define ONEWIRE_CS_ALTP 0x40000000 // Alternate Polarity Enable
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#define ONEWIRE_CS_BSIZE_M 0x00070000 // Last Byte Size
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#define ONEWIRE_CS_BSIZE_8 0x00000000 // 8 bits (1 byte)
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#define ONEWIRE_CS_BSIZE_1 0x00010000 // 1 bit
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#define ONEWIRE_CS_BSIZE_2 0x00020000 // 2 bits
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#define ONEWIRE_CS_BSIZE_3 0x00030000 // 3 bits
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#define ONEWIRE_CS_BSIZE_4 0x00040000 // 4 bits
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#define ONEWIRE_CS_BSIZE_5 0x00050000 // 5 bits
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#define ONEWIRE_CS_BSIZE_6 0x00060000 // 6 bits
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#define ONEWIRE_CS_BSIZE_7 0x00070000 // 7 bits
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#define ONEWIRE_CS_STUCK 0x00000400 // STUCK Status
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#define ONEWIRE_CS_NOATR 0x00000200 // Answer-to-Reset Status
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#define ONEWIRE_CS_BUSY 0x00000100 // Busy Status
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#define ONEWIRE_CS_SKATR 0x00000080 // Skip Answer-to-Reset Enable
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#define ONEWIRE_CS_LSAM 0x00000040 // Late Sample Enable
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#define ONEWIRE_CS_ODRV 0x00000020 // Overdrive Enable
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#define ONEWIRE_CS_SZ_M 0x00000018 // Data Operation Size
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#define ONEWIRE_CS_OP_M 0x00000006 // Operation Request
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#define ONEWIRE_CS_OP_NONE 0x00000000 // No operation
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#define ONEWIRE_CS_OP_RD 0x00000002 // Read
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#define ONEWIRE_CS_OP_WR 0x00000004 // Write
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#define ONEWIRE_CS_OP_WRRD 0x00000006 // Write/Read
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#define ONEWIRE_CS_RST 0x00000001 // Reset Request
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#define ONEWIRE_CS_SZ_S 3
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the ONEWIRE_O_TIM register.
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//
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//*****************************************************************************
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#define ONEWIRE_TIM_W1TIM_M 0xF0000000 // Value '1' Timing
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#define ONEWIRE_TIM_W0TIM_M 0x0F800000 // Value '0' Timing
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#define ONEWIRE_TIM_W0REST_M 0x00780000 // Rest Time
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#define ONEWIRE_TIM_W1SAM_M 0x00078000 // Sample Time
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#define ONEWIRE_TIM_ATRSAM_M 0x00007800 // Answer-to-Reset Sample
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#define ONEWIRE_TIM_ATRTIM_M 0x000007C0 // Answer-to-Reset/Rest Period
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#define ONEWIRE_TIM_RSTTIM_M 0x0000003F // Reset Low Time
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#define ONEWIRE_TIM_W1TIM_S 28
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#define ONEWIRE_TIM_W0TIM_S 23
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#define ONEWIRE_TIM_W0REST_S 19
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#define ONEWIRE_TIM_W1SAM_S 15
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#define ONEWIRE_TIM_ATRSAM_S 11
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#define ONEWIRE_TIM_ATRTIM_S 6
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#define ONEWIRE_TIM_RSTTIM_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the ONEWIRE_O_DATW register.
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//
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//*****************************************************************************
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#define ONEWIRE_DATW_B3_M 0xFF000000 // Upper Data Byte
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#define ONEWIRE_DATW_B2_M 0x00FF0000 // Upper Middle Data Byte
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#define ONEWIRE_DATW_B1_M 0x0000FF00 // Lower Middle Data Byte
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#define ONEWIRE_DATW_B0_M 0x000000FF // Lowest Data Byte
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#define ONEWIRE_DATW_B3_S 24
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#define ONEWIRE_DATW_B2_S 16
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#define ONEWIRE_DATW_B1_S 8
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#define ONEWIRE_DATW_B0_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the ONEWIRE_O_DATR register.
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//
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//*****************************************************************************
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#define ONEWIRE_DATR_B3_M 0xFF000000 // Upper Data Byte
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#define ONEWIRE_DATR_B2_M 0x00FF0000 // Upper Middle Data Byte
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#define ONEWIRE_DATR_B1_M 0x0000FF00 // Lower Middle Data Byte
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#define ONEWIRE_DATR_B0_M 0x000000FF // Lowest Data Byte
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#define ONEWIRE_DATR_B3_S 24
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#define ONEWIRE_DATR_B2_S 16
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#define ONEWIRE_DATR_B1_S 8
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#define ONEWIRE_DATR_B0_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the ONEWIRE_O_IM register.
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//
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//*****************************************************************************
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#define ONEWIRE_IM_DMA 0x00000010 // DMA Done Interrupt Mask
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#define ONEWIRE_IM_STUCK 0x00000008 // Stuck Status Interrupt Mask
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#define ONEWIRE_IM_NOATR 0x00000004 // No Answer-to-Reset Interrupt
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// Mask
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#define ONEWIRE_IM_OPC 0x00000002 // Operation Complete Interrupt
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// Mask
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#define ONEWIRE_IM_RST 0x00000001 // Reset Interrupt Mask
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the ONEWIRE_O_RIS register.
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//
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//*****************************************************************************
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#define ONEWIRE_RIS_DMA 0x00000010 // DMA Done Raw Interrupt Status
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#define ONEWIRE_RIS_STUCK 0x00000008 // Stuck Status Raw Interrupt
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// Status
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#define ONEWIRE_RIS_NOATR 0x00000004 // No Answer-to-Reset Raw Interrupt
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// Status
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#define ONEWIRE_RIS_OPC 0x00000002 // Operation Complete Raw Interrupt
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// Status
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#define ONEWIRE_RIS_RST 0x00000001 // Reset Raw Interrupt Status
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the ONEWIRE_O_MIS register.
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//
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//*****************************************************************************
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#define ONEWIRE_MIS_DMA 0x00000010 // DMA Done Masked Interrupt Status
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#define ONEWIRE_MIS_STUCK 0x00000008 // Stuck Status Masked Interrupt
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// Status
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#define ONEWIRE_MIS_NOATR 0x00000004 // No Answer-to-Reset Masked
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// Interrupt Status
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#define ONEWIRE_MIS_OPC 0x00000002 // Operation Complete Masked
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// Interrupt Status
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#define ONEWIRE_MIS_RST 0x00000001 // Reset Interrupt Mask
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the ONEWIRE_O_ICR register.
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//
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//*****************************************************************************
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#define ONEWIRE_ICR_DMA 0x00000010 // DMA Done Interrupt Clear
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#define ONEWIRE_ICR_STUCK 0x00000008 // Stuck Status Interrupt Clear
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#define ONEWIRE_ICR_NOATR 0x00000004 // No Answer-to-Reset Interrupt
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// Clear
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#define ONEWIRE_ICR_OPC 0x00000002 // Operation Complete Interrupt
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// Clear
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#define ONEWIRE_ICR_RST 0x00000001 // Reset Interrupt Clear
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the ONEWIRE_O_DMA register.
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//
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//*****************************************************************************
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#define ONEWIRE_DMA_SG 0x00000008 // Scatter-Gather Enable
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#define ONEWIRE_DMA_DMAOP_M 0x00000006 // uDMA Operation
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#define ONEWIRE_DMA_DMAOP_DIS 0x00000000 // uDMA disabled
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#define ONEWIRE_DMA_DMAOP_RDSNG 0x00000002 // uDMA single read: 1-Wire
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// requests uDMA to read
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// ONEWIREDATR register after each
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// read transaction
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#define ONEWIRE_DMA_DMAOP_WRMUL 0x00000004 // uDMA multiple write: 1-Wire
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// requests uDMA to load whenever
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// the ONEWIREDATW register is
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// empty
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#define ONEWIRE_DMA_DMAOP_RDMUL 0x00000006 // uDMA multiple read: An initial
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// read occurs and subsequent reads
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// start after uDMA has read the
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// ONEWIREDATR register
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#define ONEWIRE_DMA_RST 0x00000001 // uDMA Reset
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the ONEWIRE_O_PP register.
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//
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//*****************************************************************************
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#define ONEWIRE_PP_DMAP 0x00000010 // uDMA Present
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#define ONEWIRE_PP_CNT_M 0x00000003 // 1-Wire Bus Count
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#define ONEWIRE_PP_CNT_S 0
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#endif // __HW_ONEWIRE_H__
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