126 lines
5.2 KiB
C
126 lines
5.2 KiB
C
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#ifndef BCM283X_H__
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#define BCM283X_H__
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#include <rthw.h>
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#define PER_BASE (0x3F000000)
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#define PER_BASE_40000000 (0x40000000)
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/*
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* GPIO
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*/
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#define GPIO_BASE (PER_BASE + 0x200000)
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#define GPIO_GPFSEL0 HWREG32(GPIO_BASE + 0x00) /* GPIO Function Select 0 32bit R/W */
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#define GPIO_GPFSEL1 HWREG32(GPIO_BASE + 0x04) /* GPIO Function Select 1 32bit R/W */
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#define GPIO_GPFSEL2 HWREG32(GPIO_BASE + 0x08) /* GPIO Function Select 2 32bit R/W */
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#define GPIO_GPFSEL4 HWREG32(GPIO_BASE + 0x10) /* GPIO Function Select 4 32bit R/W */
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#define GPIO_GPSET0 HWREG32(GPIO_BASE + 0x1C)
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#define GPIO_GPCLR0 HWREG32(GPIO_BASE + 0x28)
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#define GPIO_GPPUD HWREG32(GPIO_BASE + 0x94) /* GPIO Pin Pull-up/down Enable */
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#define GPIO_GPPUDCLK0 HWREG32(GPIO_BASE + 0x98) /* GPIO Pin Pull-up/down Enable Clock 0 */
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#define GPIO_GPPUDCLK1 HWREG32(GPIO_BASE + 0x9C) /* GPIO Pin Pull-up/down Enable Clock 1 */
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/*
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* Interrupt Controler
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*/
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#define IRQ_BASE (PER_BASE + 0xB200)
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#define IRQ_PEND_BASIC HWREG32(IRQ_BASE + 0x00)
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#define IRQ_PEND1 HWREG32(IRQ_BASE + 0x04)
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#define IRQ_PEND2 HWREG32(IRQ_BASE + 0x08)
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#define IRQ_FIQ_CONTROL HWREG32(IRQ_BASE + 0x0C)
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#define IRQ_ENABLE1 HWREG32(IRQ_BASE + 0x10)
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#define IRQ_ENABLE2 HWREG32(IRQ_BASE + 0x14)
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#define IRQ_ENABLE_BASIC HWREG32(IRQ_BASE + 0x18)
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#define IRQ_DISABLE1 HWREG32(IRQ_BASE + 0x1C)
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#define IRQ_DISABLE2 HWREG32(IRQ_BASE + 0x20)
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#define IRQ_DISABLE_BASIC HWREG32(IRQ_BASE + 0x24)
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/*
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* System Timer
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*/
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#define STIMER_BASE (PER_BASE + 0x3000)
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#define STIMER_CS HWREG32(STIMER_BASE + 0x00)
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#define STIMER_CLO HWREG32(STIMER_BASE + 0x04)
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#define STIMER_CHI HWREG32(STIMER_BASE + 0x08)
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#define STIMER_C0 HWREG32(STIMER_BASE + 0x0C)
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#define STIMER_C1 HWREG32(STIMER_BASE + 0x10)
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#define STIMER_C2 HWREG32(STIMER_BASE + 0x14)
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#define STIMER_C3 HWREG32(STIMER_BASE + 0x18)
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/*
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* ARM Timer
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*/
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#define ARM_TIMER_BASE (PER_BASE + 0xB000)
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#define ARM_TIMER_LOAD HWREG32(ARM_TIMER_BASE + 0x400)
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#define ARM_TIMER_VALUE HWREG32(ARM_TIMER_BASE + 0x404)
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#define ARM_TIMER_CTRL HWREG32(ARM_TIMER_BASE + 0x408)
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#define ARM_TIMER_IRQCLR HWREG32(ARM_TIMER_BASE + 0x40C)
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#define ARM_TIMER_RAWIRQ HWREG32(ARM_TIMER_BASE + 0x410)
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#define ARM_TIMER_MASKIRQ HWREG32(ARM_TIMER_BASE + 0x414)
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#define ARM_TIMER_RELOAD HWREG32(ARM_TIMER_BASE + 0x418)
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#define ARM_TIMER_PREDIV HWREG32(ARM_TIMER_BASE + 0x41C)
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#define ARM_TIMER_CNTR HWREG32(ARM_TIMER_BASE + 0x420)
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/*
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* Core Timer
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*/
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#define CTIMER_CTL HWREG32(PER_BASE_40000000 + 0x00) /* Control register */
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#define CTIMER_PRE HWREG32(PER_BASE_40000000 + 0x08) /* Core timer prescaler */
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#define CTIMER_LS32B HWREG32(PER_BASE_40000000 + 0x1C) /* Core timer access LS 32 bits */
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#define CTIMER_MS32B HWREG32(PER_BASE_40000000 + 0x20) /* Core timer access MS 32 bits */
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/*
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* ARM Core Timer
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*/
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#define C0TIMER_INTCTL HWREG32(PER_BASE_40000000 + 0x40) /* Core0 timers Interrupt control */
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#define C1TIMER_INTCTL HWREG32(PER_BASE_40000000 + 0x44) /* Core1 timers Interrupt control */
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#define C2TIMER_INTCTL HWREG32(PER_BASE_40000000 + 0x48) /* Core2 timers Interrupt control */
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#define C3TIMER_INTCTL HWREG32(PER_BASE_40000000 + 0x4C) /* Core3 timers Interrupt control */
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/*
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* ARM Core Mailbox interrupt
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*/
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#define C0MB_INTCTL HWREG32(PER_BASE_40000000 + 0x50) /* Core0 Mailboxes Interrupt control */
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#define C1MB_INTCTL HWREG32(PER_BASE_40000000 + 0x54) /* Core1 Mailboxes Interrupt control */
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#define C2MB_INTCTL HWREG32(PER_BASE_40000000 + 0x58) /* Core2 Mailboxes Interrupt control */
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#define C3MB_INTCTL HWREG32(PER_BASE_40000000 + 0x5C) /* Core3 Mailboxes Interrupt control */
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/*
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* ARM Core IRQ/FIQ status
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*/
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#define C0_IRQSOURCE HWREG32(PER_BASE_40000000 + 0x60) /* Core0 IRQ Source */
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#define C1_IRQSOURCE HWREG32(PER_BASE_40000000 + 0x64) /* Core1 IRQ Source */
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#define C2_IRQSOURCE HWREG32(PER_BASE_40000000 + 0x68) /* Core2 IRQ Source */
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#define C3_IRQSOURCE HWREG32(PER_BASE_40000000 + 0x6C) /* Core3 IRQ Source */
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#define C0_FIQSOURCE HWREG32(PER_BASE_40000000 + 0x70) /* Core0 FIQ Source */
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#define C1_FIQSOURCE HWREG32(PER_BASE_40000000 + 0x74) /* Core1 FIQ Source */
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#define C2_FIQSOURCE HWREG32(PER_BASE_40000000 + 0x78) /* Core2 FIQ Source */
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#define C3_FIQSOURCE HWREG32(PER_BASE_40000000 + 0x7C) /* Core3 FIQ Source */
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#define IRQ_ARM_TIMER 0
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#define IRQ_ARM_MAILBOX 1
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#define IRQ_ARM_DB0 2
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#define IRQ_ARM_DB1 3
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#define IRQ_ARM_GPU0_HALT 4
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#define IRQ_ARM_GPU1_HALT 5
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#define IRQ_ARM_ILLEGAL_ACC1 6
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#define IRQ_ARM_ILLEGAL_ACC0 7
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#define IRQ_AUX 29
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#define IRQ_IIC_SPI_SLV 43
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#define IRQ_PWA0 45
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#define IRQ_PWA1 46
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#define IRQ_SMI 48
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#define IRQ_GPIO0 49
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#define IRQ_GPIO1 50
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#define IRQ_GPIO2 51
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#define IRQ_GPIO3 52
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#define IRQ_IIC 53
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#define IRQ_SPI 54
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#define IRQ_PCM 55
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#define IRQ_UART 57
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#endif
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