rt-thread-official/bsp/phytium/aarch64/rtconfig.h

546 lines
12 KiB
C
Raw Normal View History

#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* RT-Thread Kernel */
#define RT_NAME_MAX 16
#define RT_USING_SMP
#define RT_CPUS_NR 2
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000
#define RT_USING_HOOK
#define RT_HOOK_USING_FUNC_PTR
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 8192
#define SYSTEM_THREAD_STACK_SIZE 8192
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 8192
/* kservice optimization */
2024-05-20 15:18:22 +08:00
/* end of kservice optimization */
/* klibc optimization */
#define RT_KLIBC_USING_VSNPRINTF_LONGLONG
2024-05-20 15:18:22 +08:00
/* end of klibc optimization */
#define RT_USING_DEBUG
2024-05-20 15:18:22 +08:00
#define RT_DEBUGING_ASSERT
#define RT_DEBUGING_COLOR
2024-07-22 10:33:39 +08:00
#define RT_USING_OVERFLOW_CHECK
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
2024-05-20 15:18:22 +08:00
/* end of Inter-Thread communication */
/* Memory Management */
#define RT_PAGE_MAX_ORDER 16
#define RT_USING_SLAB
#define RT_USING_MEMHEAP
#define RT_MEMHEAP_FAST_MODE
#define RT_USING_SLAB_AS_HEAP
#define RT_USING_HEAP_ISR
#define RT_USING_HEAP
2024-05-20 15:18:22 +08:00
/* end of Memory Management */
#define RT_USING_DEVICE
#define RT_USING_SCHED_THREAD_CTX
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart1"
2024-05-20 15:18:22 +08:00
#define RT_VER_NUM 0x50200
#define RT_BACKTRACE_LEVEL_MAX_NR 32
2024-05-20 15:18:22 +08:00
/* end of RT-Thread Kernel */
2023-08-29 10:27:54 +08:00
/* AArch64 Architecture Configuration */
#define ARCH_TEXT_OFFSET 0x80000
#define ARCH_RAM_OFFSET 0x80000000
#define ARCH_SECONDARY_CPU_STACK_SIZE 4096
#define ARCH_HAVE_EFFICIENT_UNALIGNED_ACCESS
2024-07-22 10:33:39 +08:00
#define ARCH_HEAP_SIZE 0x4000000
#define ARCH_INIT_PAGE_SIZE 0x200000
2024-05-20 15:18:22 +08:00
/* end of AArch64 Architecture Configuration */
#define ARCH_CPU_64BIT
#define RT_USING_CACHE
#define RT_USING_HW_ATOMIC
#define ARCH_ARM_BOOTWITH_FLUSH_CACHE
#define RT_USING_CPU_FFS
#define ARCH_MM_MMU
#define ARCH_ARM
#define ARCH_ARM_MMU
#define ARCH_ARMV8
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 8192
#define RT_MAIN_THREAD_PRIORITY 10
#define RT_USING_MSH
#define RT_USING_FINSH
#define FINSH_USING_MSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_CMD_SIZE 80
#define MSH_USING_BUILT_IN_COMMANDS
#define FINSH_USING_DESCRIPTION
#define FINSH_ARG_MAX 10
#define FINSH_USING_OPTION_COMPLETION
/* DFS: device virtual file system */
#define RT_USING_DFS
#define DFS_USING_POSIX
#define DFS_USING_WORKDIR
#define DFS_FD_MAX 16
#define RT_USING_DFS_V1
#define DFS_FILESYSTEMS_MAX 4
#define DFS_FILESYSTEM_TYPES_MAX 4
#define RT_USING_DFS_ELMFAT
/* elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_DFS_ELM_CODE_PAGE 437
#define RT_DFS_ELM_WORD_ACCESS
#define RT_DFS_ELM_USE_LFN_3
#define RT_DFS_ELM_USE_LFN 3
#define RT_DFS_ELM_LFN_UNICODE_0
#define RT_DFS_ELM_LFN_UNICODE 0
#define RT_DFS_ELM_MAX_LFN 255
#define RT_DFS_ELM_DRIVES 2
#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
#define RT_DFS_ELM_REENTRANT
#define RT_DFS_ELM_MUTEX_TIMEOUT 3000
2024-05-20 15:18:22 +08:00
/* end of elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_USING_DFS_DEVFS
#define RT_USING_DFS_RAMFS
2024-05-20 15:18:22 +08:00
/* end of DFS: device virtual file system */
/* Device Drivers */
2024-07-22 10:33:39 +08:00
#define RT_USING_DEV_BUS
#define RT_USING_DEVICE_IPC
#define RT_UNAMED_PIPE_NUMBER 64
#define RT_USING_SYSTEM_WORKQUEUE
#define RT_SYSTEM_WORKQUEUE_STACKSIZE 8192
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_CAN
2024-05-20 15:55:43 +08:00
#define RT_CAN_USING_HDR
#define RT_CAN_USING_CANFD
#define RT_USING_I2C
#define RT_USING_I2C_BITOPS
#define RT_USING_NULL
#define RT_USING_ZERO
#define RT_USING_RANDOM
#define RT_USING_PWM
#define RT_USING_RTC
#define RT_USING_SDIO
#define RT_SDIO_STACK_SIZE 8192
#define RT_SDIO_THREAD_PRIORITY 15
#define RT_MMCSD_STACK_SIZE 8192
#define RT_MMCSD_THREAD_PREORITY 22
#define RT_MMCSD_MAX_PARTITION 16
#define RT_USING_SPI
#define RT_USING_QSPI
#define RT_USING_PIN
#define RT_USING_KTIME
#define RT_USING_CHERRYUSB
#define RT_CHERRYUSB_HOST
#define RT_CHERRYUSB_HOST_XHCI
#define RT_CHERRYUSB_HOST_HID
#define RT_CHERRYUSB_HOST_MSC
2024-09-06 06:18:27 +08:00
#define RT_LWIP_PBUF_POOL_BUFSIZE 1700
2024-05-20 15:18:22 +08:00
/* end of Device Drivers */
/* C/C++ and POSIX layer */
2023-08-29 10:27:54 +08:00
/* ISO-ANSI C layer */
/* Timezone and Daylight Saving Time */
#define RT_LIBC_USING_LIGHT_TZ_DST
#define RT_LIBC_TZ_DEFAULT_HOUR 8
#define RT_LIBC_TZ_DEFAULT_MIN 0
#define RT_LIBC_TZ_DEFAULT_SEC 0
2024-05-20 15:18:22 +08:00
/* end of Timezone and Daylight Saving Time */
/* end of ISO-ANSI C layer */
/* POSIX (Portable Operating System Interface) layer */
#define RT_USING_POSIX_FS
#define RT_USING_POSIX_DEVIO
#define RT_USING_POSIX_STDIO
#define RT_USING_POSIX_TERMIOS
#define RT_USING_POSIX_DELAY
#define RT_USING_POSIX_CLOCK
#define RT_USING_POSIX_TIMER
/* Interprocess Communication (IPC) */
/* Socket is in the 'Network' category */
2024-05-20 15:18:22 +08:00
/* end of Interprocess Communication (IPC) */
/* end of POSIX (Portable Operating System Interface) layer */
/* end of C/C++ and POSIX layer */
/* Network */
#define RT_USING_SAL
#define SAL_INTERNET_CHECK
/* Docking with protocol stacks */
#define SAL_USING_LWIP
2024-05-20 15:18:22 +08:00
/* end of Docking with protocol stacks */
#define SAL_USING_POSIX
#define RT_USING_NETDEV
#define NETDEV_USING_IFCONFIG
#define NETDEV_USING_PING
#define NETDEV_USING_NETSTAT
#define NETDEV_USING_AUTO_DEFAULT
#define NETDEV_IPV4 1
#define NETDEV_IPV6 0
#define RT_USING_LWIP
#define RT_USING_LWIP212
#define RT_USING_LWIP_VER_NUM 0x20102
#define RT_LWIP_MEM_ALIGNMENT 64
#define RT_LWIP_IGMP
#define RT_LWIP_ICMP
#define RT_LWIP_DNS
/* Static IPv4 Address */
#define RT_LWIP_IPADDR "192.168.4.10"
#define RT_LWIP_GWADDR "192.168.4.1"
#define RT_LWIP_MSKADDR "255.255.255.0"
2024-05-20 15:18:22 +08:00
/* end of Static IPv4 Address */
#define RT_LWIP_UDP
#define RT_LWIP_TCP
#define RT_LWIP_RAW
#define RT_MEMP_NUM_NETCONN 8
#define RT_LWIP_PBUF_NUM 512
#define RT_LWIP_RAW_PCB_NUM 4
#define RT_LWIP_UDP_PCB_NUM 4
#define RT_LWIP_TCP_PCB_NUM 4
#define RT_LWIP_TCP_SEG_NUM 40
#define RT_LWIP_TCP_SND_BUF 8196
#define RT_LWIP_TCP_WND 8196
2024-05-20 17:53:49 +08:00
#define RT_LWIP_TCPTHREAD_PRIORITY 16
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
#define RT_LWIP_TCPTHREAD_STACKSIZE 16184
#define RT_LWIP_ETHTHREAD_PRIORITY 12
#define RT_LWIP_ETHTHREAD_STACKSIZE 8192
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
2024-05-20 15:55:43 +08:00
#define RT_LWIP_REASSEMBLY_FRAG
#define LWIP_NETIF_STATUS_CALLBACK 1
#define LWIP_NETIF_LINK_CALLBACK 1
#define RT_LWIP_NETIF_NAMESIZE 6
#define SO_REUSE 1
#define LWIP_SO_RCVTIMEO 1
#define LWIP_SO_SNDTIMEO 1
#define LWIP_SO_RCVBUF 1
#define LWIP_SO_LINGER 0
#define LWIP_NETIF_LOOPBACK 0
#define RT_LWIP_USING_PING
2024-05-20 15:18:22 +08:00
/* end of Network */
/* Memory protection */
2024-05-20 15:18:22 +08:00
/* end of Memory protection */
/* Utilities */
#define RT_USING_RYM
#define YMODEM_USING_FILE_TRANSFER
#define RT_USING_RESOURCE_ID
#define RT_USING_ADT
#define RT_USING_ADT_AVL
#define RT_USING_ADT_BITMAP
#define RT_USING_ADT_HASHMAP
#define RT_USING_ADT_REF
2024-05-20 15:18:22 +08:00
/* end of Utilities */
2024-07-22 10:33:39 +08:00
/* Using USB legacy version */
/* end of Using USB legacy version */
2024-05-20 15:18:22 +08:00
/* end of RT-Thread Components */
/* RT-Thread Utestcases */
2024-05-20 15:18:22 +08:00
/* end of RT-Thread Utestcases */
/* RT-Thread online packages */
/* IoT - internet of things */
/* Wi-Fi */
/* Marvell WiFi */
2024-05-20 15:18:22 +08:00
/* end of Marvell WiFi */
/* Wiced WiFi */
2024-05-20 15:18:22 +08:00
/* end of Wiced WiFi */
/* CYW43012 WiFi */
/* end of CYW43012 WiFi */
/* BL808 WiFi */
/* end of BL808 WiFi */
/* CYW43439 WiFi */
/* end of CYW43439 WiFi */
2024-05-20 15:18:22 +08:00
/* end of Wi-Fi */
/* IoT Cloud */
2024-05-20 15:18:22 +08:00
/* end of IoT Cloud */
/* end of IoT - internet of things */
/* security packages */
2024-05-20 15:18:22 +08:00
/* end of security packages */
/* language packages */
/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
2024-05-20 15:18:22 +08:00
/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* XML: Extensible Markup Language */
2024-05-20 15:18:22 +08:00
/* end of XML: Extensible Markup Language */
/* end of language packages */
/* multimedia packages */
/* LVGL: powerful and easy-to-use embedded GUI library */
2024-05-20 15:18:22 +08:00
/* end of LVGL: powerful and easy-to-use embedded GUI library */
/* u8g2: a monochrome graphic library */
2024-05-20 15:18:22 +08:00
/* end of u8g2: a monochrome graphic library */
/* end of multimedia packages */
/* tools packages */
2024-05-20 15:18:22 +08:00
/* end of tools packages */
/* system packages */
/* enhanced kernel services */
2024-05-20 15:18:22 +08:00
/* end of enhanced kernel services */
/* acceleration: Assembly language or algorithmic acceleration packages */
2024-05-20 15:18:22 +08:00
/* end of acceleration: Assembly language or algorithmic acceleration packages */
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
2024-05-20 15:18:22 +08:00
/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* Micrium: Micrium software products porting for RT-Thread */
2024-05-20 15:18:22 +08:00
/* end of Micrium: Micrium software products porting for RT-Thread */
/* end of system packages */
/* peripheral libraries and drivers */
/* HAL & SDK Drivers */
/* STM32 HAL & SDK Drivers */
/* end of STM32 HAL & SDK Drivers */
/* Kendryte SDK */
/* end of Kendryte SDK */
/* end of HAL & SDK Drivers */
/* sensors drivers */
2024-05-20 15:18:22 +08:00
/* end of sensors drivers */
/* touch drivers */
2024-05-20 15:18:22 +08:00
/* end of touch drivers */
/* end of peripheral libraries and drivers */
/* AI packages */
2024-05-20 15:18:22 +08:00
/* end of AI packages */
/* Signal Processing and Control Algorithm Packages */
2024-05-20 15:18:22 +08:00
/* end of Signal Processing and Control Algorithm Packages */
/* miscellaneous packages */
/* project laboratory */
2024-05-20 15:18:22 +08:00
/* end of project laboratory */
/* samples: kernel and components samples */
#define PKG_USING_KERNEL_SAMPLES
#define PKG_USING_KERNEL_SAMPLES_LATEST_VERSION
#define PKG_USING_KERNEL_SAMPLES_EN
2024-05-20 15:18:22 +08:00
/* end of samples: kernel and components samples */
/* entertainment: terminal games and other interesting software packages */
2024-05-20 15:18:22 +08:00
/* end of entertainment: terminal games and other interesting software packages */
/* end of miscellaneous packages */
/* Arduino libraries */
/* Projects and Demos */
2024-05-20 15:18:22 +08:00
/* end of Projects and Demos */
/* Sensors */
2024-05-20 15:18:22 +08:00
/* end of Sensors */
/* Display */
2024-05-20 15:18:22 +08:00
/* end of Display */
/* Timing */
2024-05-20 15:18:22 +08:00
/* end of Timing */
/* Data Processing */
2024-05-20 15:18:22 +08:00
/* end of Data Processing */
/* Data Storage */
/* Communication */
2024-05-20 15:18:22 +08:00
/* end of Communication */
/* Device Control */
2024-05-20 15:18:22 +08:00
/* end of Device Control */
/* Other */
2024-05-20 15:18:22 +08:00
/* end of Other */
/* Signal IO */
2024-05-20 15:18:22 +08:00
/* end of Signal IO */
/* Uncategorized */
2024-05-20 15:18:22 +08:00
/* end of Arduino libraries */
/* end of RT-Thread online packages */
/* Hardware Drivers */
/* On-chip Peripheral Drivers */
#define BSP_USING_IOPAD
#define BSP_USING_UART
#define RT_USING_UART0
#define RT_USING_UART1
#define BSP_USING_SPI
#define RT_USING_SPIM2
2024-05-20 15:55:43 +08:00
#define BSP_USING_CAN
#define RT_USING_CANFD
#define RT_USING_CAN0
#define RT_USING_CAN1
#define BSP_USING_GPIO
#define BSP_USING_QSPI
#define RT_USING_QSPI0
#define USING_QSPI_CHANNEL0
#define BSP_USING_ETH
2024-05-20 17:53:49 +08:00
#define BSP_USING_PWM
#define BSP_USING_I2C
#define I2C_USE_MIO
2024-05-20 15:55:43 +08:00
#define RT_USING_MIO15
#define BSP_USING_SDIF
#define BSP_USING_SDCARD_FATFS
2024-05-20 15:55:43 +08:00
#define USING_SDIF0
#define USE_SDIF0_EMMC
#define USING_SDIF1
#define USE_SDIF1_TF
#define BSP_USING_DC
2024-07-22 10:33:39 +08:00
#define RT_USING_DC_CHANNEL0
2024-05-20 15:55:43 +08:00
#define RT_USING_DC_CHANNEL1
2024-05-20 15:18:22 +08:00
/* end of On-chip Peripheral Drivers */
/* Board extended module Drivers */
2024-05-20 15:18:22 +08:00
/* end of Hardware Drivers */
#define BSP_USING_GIC
#define BSP_USING_GICV3
#define PHYTIUM_ARCH_AARCH64
#define ARM_SPI_BIND_CPU_ID 0
/* Standalone Setting */
#define TARGET_ARMV8_AARCH64
/* Soc configuration */
#define TARGET_E2000D
2024-05-20 15:55:43 +08:00
#define SOC_NAME "e2000"
#define TARGET_TYPE_NAME "d"
#define SOC_CORE_NUM 2
#define F32BIT_MEMORY_ADDRESS 0x80000000
#define F32BIT_MEMORY_LENGTH 0x80000000
#define F64BIT_MEMORY_ADDRESS 0x2000000000
#define F64BIT_MEMORY_LENGTH 0x800000000
#define TARGET_E2000
#define DEFAULT_DEBUG_PRINT_UART1
2024-05-20 15:18:22 +08:00
/* end of Soc configuration */
/* Board Configuration */
#define E2000D_DEMO_BOARD
2024-05-20 15:55:43 +08:00
#define BOARD_NAME "demo"
/* IO mux configuration when board start up */
2024-05-20 15:18:22 +08:00
/* end of IO mux configuration when board start up */
/* end of Board Configuration */
/* Sdk common configuration */
#define ELOG_LINE_BUF_SIZE 0x100
#define LOG_DEBUG
2024-05-20 15:18:22 +08:00
/* end of Sdk common configuration */
/* end of Standalone Setting */
#endif