121 lines
4.1 KiB
C
121 lines
4.1 KiB
C
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/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-01-08 brightsally first version
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*/
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#ifndef _ATMEL_NAND_H_
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#define _ATMEL_NAND_H_
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/* NAND flash */
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#define DATA_PART_ADDR 0x900000 /*nand0=0-9MB;nand1=9MB-END*/
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#define AT91C_BASE_CCFG 0xffffef14
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#define CCFG_EBICSA 0x08 /* EBI Chip Select Assignement Register */
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#define AT91C_EBI_CS3A_SM (0x1UL << 3)
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#define AT91C_BASE_SMC 0xffffec00
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#define AT91C_BASE_PMC 0xfffffc00
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#define SMC_SETUP3 0x30 /* Setup Register for CS 3 */
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#define SMC_PULSE3 0x34 /* Pulse Register for CS 3 */
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#define SMC_CYCLE3 0x38 /* Cycle Register for CS 3 */
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#define SMC_CTRL3 0x3C /* Control Register for CS 3 */
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#define AT91C_SMC_NWESETUP_(x) ((x) << 0)
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#define AT91C_SMC_NCS_WRSETUP_(x) ((x) << 8)
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#define AT91C_SMC_NRDSETUP_(x) ((x) << 16)
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#define AT91C_SMC_NCS_RDSETUP_(x) ((x) << 24)
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#define AT91C_SMC_NWEPULSE_(x) ((x) << 0)
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#define AT91C_SMC_NCS_WRPULSE_(x) ((x) << 8)
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#define AT91C_SMC_NRDPULSE_(x) ((x) << 16)
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#define AT91C_SMC_NCS_RDPULSE_(x) ((x) << 24)
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#define AT91C_SMC_NWECYCLE_(x) ((x) << 0)
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#define AT91C_SMC_NRDCYCLE_(x) ((x) << 16)
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#define AT91C_SMC_READMODE (0x1UL << 0)
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#define AT91C_SMC_WRITEMODE (0x1UL << 1)
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#define AT91C_SMC_NWAITM (0x3UL << 4)
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#define AT91C_SMC_DBW_WIDTH_BITS_8 (0x0UL << 12)
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#define AT91C_SMC_DBW_WIDTH_BITS_16 (0x1UL << 12)
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#define AT91C_SMC_DBW_WIDTH_BITS_32 (0x2UL << 12)
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#define AT91C_SMC_TDF (0xFUL << 16)
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#define AT91_SMC_TDF_(x) ((x) << 16)
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#define CMD_STATUS 0x70
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#define STATUS_READY (0x01 << 6) /* Status code for Ready */
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#define STATUS_ERROR (0x01 << 0) /* Status code for Error */
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/* Nand flash commands */
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#define CMD_READID 0x90
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#define CMD_READ_1 0x00
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#define CMD_READ_2 0x30
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#define CMD_READ_A0 0x00
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#define CMD_READ_A1 0x01
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#define CMD_READ_C 0x50
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#define CMD_WRITE_A 0x00
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#define CMD_WRITE_C 0x50
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#define CMD_WRITE_1 0x80
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#define CMD_WRITE_2 0x10
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#define CMD_ERASE_1 0x60
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#define CMD_ERASE_2 0xD0
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/* read/write/move page */
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#define CMD_REG 0x40400000
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#define ADDR_REG 0x40200000
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#define DATA_REG 0x40000000
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/*Values returned by the CheckBlock() function
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GOOD = RT_EOK=0
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BAD = -1
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*/
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#define BADBLOCK -RT_ERROR //-1
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#define GOODBLOCK RT_EOK //0
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struct nand_oobfree
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{
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unsigned int offset;
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unsigned int length;
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};
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struct nand_ecclayout
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{
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unsigned int eccbytes;
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unsigned int eccpos[680];
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unsigned int oobavail;
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struct nand_oobfree oobfree[32];
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};
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struct nand_chip_id
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{
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unsigned short chip_id; /* Nand Chip ID */
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unsigned short numblocks; //0x1000=4096=4K //4K*16K=64M
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unsigned int blocksize; //0x4000=16K //SECTOR
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unsigned short pagesize; //0X200=512 //1 BLOCK has pages=16K/512=32
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unsigned char oobsize; //0X10=16
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unsigned char buswidth;
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};
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static struct nand_chip_id nand_ids[] =
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{
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/* Samsung 32MB 8Bit SMALL BLOCK*/
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{0xec75, 0x800, 0x4000, 0x200, 0x10, 0x0}, //32M
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{0xec35, 0x800, 0x4000, 0x200, 0x10, 0x0}, //32M
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{0xec36, 0x1000, 0x4000, 0x200, 0x10, 0x0}, //4K*16K=64M
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/* Samsung 128MB 8bit BIG BLOCK*/
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{0xeca1, 0x400, 0x20000, 0x800, 0x40, 0x0}, //128M
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{0,}
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};
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int rt_hw_mtd_nand_init(void);
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#endif
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