557 lines
15 KiB
C
557 lines
15 KiB
C
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/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-03-02 FMD-AE first version
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*/
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#include <board.h>
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#include "drv_gpio.h"
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#ifdef RT_USING_PIN
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#define PIN_NUM(port, no) (((((port) & 0xFu) << 4) | ((no) & 0xFu)))
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#define PIN_PORT(pin) ((uint8_t)(((pin) >> 4) & 0xFu))
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#define PIN_NO(pin) ((uint8_t)((pin) & 0xFu))
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#define PIN_FTPORT(pin) ((GPIO_TypeDef *)(GPIOA_BASE +(0x400u * PIN_PORT(pin))))
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#define PIN_FTPIN(pin) ((uint16_t)(1u << PIN_NO(pin)))
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#if defined(GPIOF)
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#define __FT32_PORT_MAX 6u
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#elif defined(GPIOE)
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#define __FT32_PORT_MAX 5u
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#elif defined(GPIOD)
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#define __FT32_PORT_MAX 4u
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#elif defined(GPIOC)
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#define __FT32_PORT_MAX 3u
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#elif defined(GPIOB)
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#define __FT32_PORT_MAX 2u
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#elif defined(GPIOA)
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#define __FT32_PORT_MAX 1u
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#else
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#define __FT32_PORT_MAX 0u
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#error Unsupported FT32 GPIO peripheral.
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#endif
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#define PIN_STPORT_MAX __FT32_PORT_MAX
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static const struct pin_irq_map pin_irq_map[] =
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{
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#if defined(SOC_SERIES_FT32F0)
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{GPIO_Pin_0, EXTI0_1_IRQn},
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{GPIO_Pin_1, EXTI0_1_IRQn},
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{GPIO_Pin_2, EXTI2_3_IRQn},
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{GPIO_Pin_3, EXTI2_3_IRQn},
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{GPIO_Pin_4, EXTI4_15_IRQn},
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{GPIO_Pin_5, EXTI4_15_IRQn},
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{GPIO_Pin_6, EXTI4_15_IRQn},
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{GPIO_Pin_7, EXTI4_15_IRQn},
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{GPIO_Pin_8, EXTI4_15_IRQn},
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{GPIO_Pin_9, EXTI4_15_IRQn},
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{GPIO_Pin_10, EXTI4_15_IRQn},
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{GPIO_Pin_11, EXTI4_15_IRQn},
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{GPIO_Pin_12, EXTI4_15_IRQn},
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{GPIO_Pin_13, EXTI4_15_IRQn},
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{GPIO_Pin_14, EXTI4_15_IRQn},
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{GPIO_Pin_15, EXTI4_15_IRQn},
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#endif
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};
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static struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
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{
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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};
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static uint32_t pin_irq_enable_mask = 0;
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#define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
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static rt_base_t ft32_pin_get(const char *name)
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{
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rt_base_t pin = 0;
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int hw_port_num, hw_pin_num = 0;
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int i, name_len;
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name_len = rt_strlen(name);
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if ((name_len < 4) || (name_len >= 6))
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{
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return -RT_EINVAL;
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}
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if ((name[0] != 'P') || (name[2] != '.'))
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{
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return -RT_EINVAL;
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}
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if ((name[1] >= 'A') && (name[1] <= 'Z'))
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{
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hw_port_num = (int)(name[1] - 'A');
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}
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else
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{
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return -RT_EINVAL;
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}
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for (i = 3; i < name_len; i++)
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{
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hw_pin_num *= 10;
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hw_pin_num += name[i] - '0';
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}
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pin = PIN_NUM(hw_port_num, hw_pin_num);
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return pin;
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}
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static void ft32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
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{
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GPIO_TypeDef *gpio_port;
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uint16_t gpio_pin;
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if (PIN_PORT(pin) < PIN_STPORT_MAX)
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{
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gpio_port = PIN_FTPORT(pin);
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gpio_pin = PIN_FTPIN(pin);
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GPIO_WriteBit(gpio_port, gpio_pin, (BitAction)value);
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}
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}
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static int ft32_pin_read(rt_device_t dev, rt_base_t pin)
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{
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GPIO_TypeDef *gpio_port;
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uint16_t gpio_pin;
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int value = PIN_LOW;
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if (PIN_PORT(pin) < PIN_STPORT_MAX)
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{
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gpio_port = PIN_FTPORT(pin);
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gpio_pin = PIN_FTPIN(pin);
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value = GPIO_ReadInputDataBit(gpio_port, gpio_pin);
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}
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return value;
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}
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static void ft32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
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{
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GPIO_InitTypeDef GPIO_InitStruct;
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if (PIN_PORT(pin) >= PIN_STPORT_MAX)
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{
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return;
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}
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/* Configure GPIO_InitStructure */
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GPIO_InitStruct.GPIO_Pin = PIN_FTPIN(pin);
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GPIO_InitStruct.GPIO_Mode = GPIO_Mode_OUT;
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GPIO_InitStruct.GPIO_PuPd = GPIO_PuPd_NOPULL;
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GPIO_InitStruct.GPIO_Speed = GPIO_Speed_Level_3;
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if (mode == PIN_MODE_OUTPUT)
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{
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/* output setting */
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GPIO_InitStruct.GPIO_Mode = GPIO_Mode_OUT;
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GPIO_InitStruct.GPIO_PuPd = GPIO_PuPd_NOPULL;
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}
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else if (mode == PIN_MODE_INPUT)
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{
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/* input setting: not pull. */
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GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IN;
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GPIO_InitStruct.GPIO_PuPd = GPIO_PuPd_NOPULL;
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}
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else if (mode == PIN_MODE_INPUT_PULLUP)
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{
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/* input setting: pull up. */
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GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IN;
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GPIO_InitStruct.GPIO_PuPd = GPIO_PuPd_UP;
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}
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else if (mode == PIN_MODE_INPUT_PULLDOWN)
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{
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/* input setting: pull down. */
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GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IN;
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GPIO_InitStruct.GPIO_PuPd = GPIO_PuPd_DOWN;
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}
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else if (mode == PIN_MODE_OUTPUT_OD)
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{
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}
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GPIO_Init(PIN_FTPORT(pin), &GPIO_InitStruct);
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}
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rt_inline rt_int32_t bit2bitno(rt_uint32_t bit)
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{
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int i;
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for (i = 0; i < 32; i++)
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{
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if ((0x01 << i) == bit)
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{
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return i;
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}
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}
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return -1;
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}
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rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit)
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{
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rt_int32_t mapindex = bit2bitno(pinbit);
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if (mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map))
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{
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return RT_NULL;
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}
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return &pin_irq_map[mapindex];
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};
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static rt_err_t ft32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
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rt_uint32_t mode, void (*hdr)(void *args), void *args)
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{
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rt_base_t level;
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rt_int32_t irqindex = -1;
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if (PIN_PORT(pin) >= PIN_STPORT_MAX)
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{
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return -RT_ENOSYS;
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}
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irqindex = bit2bitno(PIN_FTPIN(pin));
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if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
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{
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return RT_ENOSYS;
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}
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level = rt_hw_interrupt_disable();
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if (pin_irq_hdr_tab[irqindex].pin == pin &&
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pin_irq_hdr_tab[irqindex].hdr == hdr &&
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pin_irq_hdr_tab[irqindex].mode == mode &&
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pin_irq_hdr_tab[irqindex].args == args)
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{
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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if (pin_irq_hdr_tab[irqindex].pin != -1)
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{
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rt_hw_interrupt_enable(level);
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return RT_EBUSY;
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}
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pin_irq_hdr_tab[irqindex].pin = pin;
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pin_irq_hdr_tab[irqindex].hdr = hdr;
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pin_irq_hdr_tab[irqindex].mode = mode;
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pin_irq_hdr_tab[irqindex].args = args;
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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static rt_err_t ft32_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
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{
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rt_base_t level;
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rt_int32_t irqindex = -1;
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if (PIN_PORT(pin) >= PIN_STPORT_MAX)
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{
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return -RT_ENOSYS;
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}
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irqindex = bit2bitno(PIN_FTPIN(pin));
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if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
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{
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return RT_ENOSYS;
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}
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level = rt_hw_interrupt_disable();
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if (pin_irq_hdr_tab[irqindex].pin == -1)
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{
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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pin_irq_hdr_tab[irqindex].pin = -1;
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pin_irq_hdr_tab[irqindex].hdr = RT_NULL;
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pin_irq_hdr_tab[irqindex].mode = 0;
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pin_irq_hdr_tab[irqindex].args = RT_NULL;
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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static void rt_gpio_deinit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
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{
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uint32_t position = 0x00u;
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uint32_t iocurrent;
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uint32_t tmp;
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/* Configure the port pins */
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while ((GPIO_Pin >> position) != 0x00u)
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{
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/* Get current io position */
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iocurrent = (GPIO_Pin) & (1uL << position);
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if (iocurrent != 0x00u)
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{
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/*------------------------- EXTI Mode Configuration --------------------*/
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/* Clear the External Interrupt or Event for the current IO */
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tmp = SYSCFG->EXTICR[position >> 2u];
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tmp &= (0x0FuL << (4u * (position & 0x03u)));
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if (tmp == (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u))))
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{
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/* Clear EXTI line configuration */
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EXTI->IMR &= ~((uint32_t)iocurrent);
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EXTI->EMR &= ~((uint32_t)iocurrent);
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/* Clear Rising Falling edge configuration */
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EXTI->RTSR &= ~((uint32_t)iocurrent);
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EXTI->FTSR &= ~((uint32_t)iocurrent);
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/* Configure the External Interrupt or event for the current IO */
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tmp = 0x0FuL << (4u * (position & 0x03u));
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SYSCFG->EXTICR[position >> 2u] &= ~tmp;
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}
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/*------------------------- GPIO Mode Configuration --------------------*/
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/* Configure IO Direction in Input Floating Mode */
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GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2u));
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/* Configure the default Alternate Function in current IO */
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GPIOx->AFR[position >> 3u] &= ~(0xFu << ((uint32_t)(position & 0x07u) * 4u)) ;
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/* Deactivate the Pull-up and Pull-down resistor for the current IO */
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GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2u));
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/* Configure the default value IO Output Type */
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GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ;
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/* Configure the default value for IO Speed */
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GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2u));
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}
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position++;
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}
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}
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static rt_err_t ft32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
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rt_uint32_t enabled)
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{
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const struct pin_irq_map *irqmap;
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rt_base_t level;
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rt_int32_t irqindex = -1;
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GPIO_InitTypeDef GPIO_InitStruct;
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EXTI_InitTypeDef EXTI_InitStructure;
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if (PIN_PORT(pin) >= PIN_STPORT_MAX)
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{
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return -RT_ENOSYS;
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}
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if (enabled == PIN_IRQ_ENABLE)
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|
{
|
||
|
|
irqindex = bit2bitno(PIN_FTPIN(pin));
|
||
|
|
if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
|
||
|
|
{
|
||
|
|
return RT_ENOSYS;
|
||
|
|
}
|
||
|
|
|
||
|
|
level = rt_hw_interrupt_disable();
|
||
|
|
|
||
|
|
if (pin_irq_hdr_tab[irqindex].pin == -1)
|
||
|
|
{
|
||
|
|
rt_hw_interrupt_enable(level);
|
||
|
|
return RT_ENOSYS;
|
||
|
|
}
|
||
|
|
|
||
|
|
irqmap = &pin_irq_map[irqindex];
|
||
|
|
|
||
|
|
RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
|
||
|
|
SYSCFG_EXTILineConfig(PIN_PORT(pin), PIN_NO(pin));
|
||
|
|
|
||
|
|
GPIO_InitStruct.GPIO_Pin = PIN_FTPIN(pin);
|
||
|
|
GPIO_InitStruct.GPIO_Speed = GPIO_Speed_Level_3;
|
||
|
|
GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IN;
|
||
|
|
switch (pin_irq_hdr_tab[irqindex].mode)
|
||
|
|
{
|
||
|
|
case PIN_IRQ_MODE_RISING:
|
||
|
|
GPIO_InitStruct.GPIO_PuPd = GPIO_PuPd_DOWN;
|
||
|
|
EXTI_InitStructure.EXTI_Line = PIN_FTPIN(pin);
|
||
|
|
EXTI_InitStructure.EXTI_LineCmd = ENABLE;
|
||
|
|
EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
|
||
|
|
EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
|
||
|
|
break;
|
||
|
|
case PIN_IRQ_MODE_FALLING:
|
||
|
|
GPIO_InitStruct.GPIO_PuPd = GPIO_PuPd_UP;
|
||
|
|
EXTI_InitStructure.EXTI_Line = PIN_FTPIN(pin);
|
||
|
|
EXTI_InitStructure.EXTI_LineCmd = ENABLE;
|
||
|
|
EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
|
||
|
|
EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;
|
||
|
|
break;
|
||
|
|
case PIN_IRQ_MODE_RISING_FALLING:
|
||
|
|
GPIO_InitStruct.GPIO_PuPd = GPIO_PuPd_NOPULL;
|
||
|
|
EXTI_InitStructure.EXTI_Line = PIN_FTPIN(pin);
|
||
|
|
EXTI_InitStructure.EXTI_LineCmd = ENABLE;
|
||
|
|
EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
|
||
|
|
EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising_Falling;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
GPIO_Init(PIN_FTPORT(pin), &GPIO_InitStruct);
|
||
|
|
EXTI_Init(&EXTI_InitStructure);
|
||
|
|
|
||
|
|
NVIC_SetPriority(irqmap->irqno, 5);
|
||
|
|
NVIC_EnableIRQ(irqmap->irqno);
|
||
|
|
pin_irq_enable_mask |= irqmap->pinbit;
|
||
|
|
|
||
|
|
rt_hw_interrupt_enable(level);
|
||
|
|
}
|
||
|
|
else if (enabled == PIN_IRQ_DISABLE)
|
||
|
|
{
|
||
|
|
irqmap = get_pin_irq_map(PIN_FTPIN(pin));
|
||
|
|
if (irqmap == RT_NULL)
|
||
|
|
{
|
||
|
|
return RT_ENOSYS;
|
||
|
|
}
|
||
|
|
|
||
|
|
level = rt_hw_interrupt_disable();
|
||
|
|
|
||
|
|
rt_gpio_deinit(PIN_FTPORT(pin), PIN_FTPIN(pin));
|
||
|
|
|
||
|
|
pin_irq_enable_mask &= ~irqmap->pinbit;
|
||
|
|
|
||
|
|
|
||
|
|
#if defined(SOC_SERIES_FT32F0)
|
||
|
|
if ((irqmap->pinbit >= GPIO_Pin_0) && (irqmap->pinbit <= GPIO_Pin_1))
|
||
|
|
{
|
||
|
|
if (!(pin_irq_enable_mask & (GPIO_Pin_0 | GPIO_Pin_1)))
|
||
|
|
{
|
||
|
|
NVIC_DisableIRQ(irqmap->irqno);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else if ((irqmap->pinbit >= GPIO_Pin_2) && (irqmap->pinbit <= GPIO_Pin_3))
|
||
|
|
{
|
||
|
|
if (!(pin_irq_enable_mask & (GPIO_Pin_2 | GPIO_Pin_3)))
|
||
|
|
{
|
||
|
|
NVIC_DisableIRQ(irqmap->irqno);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else if ((irqmap->pinbit >= GPIO_Pin_4) && (irqmap->pinbit <= GPIO_Pin_15))
|
||
|
|
{
|
||
|
|
if (!(pin_irq_enable_mask & (GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_6 | GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 |
|
||
|
|
GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15)))
|
||
|
|
{
|
||
|
|
NVIC_DisableIRQ(irqmap->irqno);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
NVIC_DisableIRQ(irqmap->irqno);
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif
|
||
|
|
rt_hw_interrupt_enable(level);
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
return -RT_ENOSYS;
|
||
|
|
}
|
||
|
|
|
||
|
|
return RT_EOK;
|
||
|
|
}
|
||
|
|
const static struct rt_pin_ops _ft32_pin_ops =
|
||
|
|
{
|
||
|
|
ft32_pin_mode,
|
||
|
|
ft32_pin_write,
|
||
|
|
ft32_pin_read,
|
||
|
|
ft32_pin_attach_irq,
|
||
|
|
ft32_pin_dettach_irq,
|
||
|
|
ft32_pin_irq_enable,
|
||
|
|
ft32_pin_get,
|
||
|
|
};
|
||
|
|
|
||
|
|
rt_inline void pin_irq_hdr(int irqno)
|
||
|
|
{
|
||
|
|
if (pin_irq_hdr_tab[irqno].hdr)
|
||
|
|
{
|
||
|
|
pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
void GPIO_EXTI_Callback(uint16_t GPIO_Pin)
|
||
|
|
{
|
||
|
|
pin_irq_hdr(bit2bitno(GPIO_Pin));
|
||
|
|
}
|
||
|
|
|
||
|
|
void GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
|
||
|
|
{
|
||
|
|
/* EXTI line interrupt detected */
|
||
|
|
if (__GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u)
|
||
|
|
{
|
||
|
|
__GPIO_EXTI_CLEAR_IT(GPIO_Pin);
|
||
|
|
GPIO_EXTI_Callback(GPIO_Pin);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
#if defined(SOC_SERIES_FT32F0)
|
||
|
|
void EXTI0_1_IRQHandler(void)
|
||
|
|
{
|
||
|
|
rt_interrupt_enter();
|
||
|
|
GPIO_EXTI_IRQHandler(GPIO_Pin_0);
|
||
|
|
GPIO_EXTI_IRQHandler(GPIO_Pin_1);
|
||
|
|
rt_interrupt_leave();
|
||
|
|
}
|
||
|
|
|
||
|
|
void EXTI2_3_IRQHandler(void)
|
||
|
|
{
|
||
|
|
rt_interrupt_enter();
|
||
|
|
GPIO_EXTI_IRQHandler(GPIO_Pin_2);
|
||
|
|
GPIO_EXTI_IRQHandler(GPIO_Pin_3);
|
||
|
|
rt_interrupt_leave();
|
||
|
|
}
|
||
|
|
void EXTI4_15_IRQHandler(void)
|
||
|
|
{
|
||
|
|
rt_interrupt_enter();
|
||
|
|
GPIO_EXTI_IRQHandler(GPIO_Pin_4);
|
||
|
|
GPIO_EXTI_IRQHandler(GPIO_Pin_5);
|
||
|
|
GPIO_EXTI_IRQHandler(GPIO_Pin_6);
|
||
|
|
GPIO_EXTI_IRQHandler(GPIO_Pin_7);
|
||
|
|
GPIO_EXTI_IRQHandler(GPIO_Pin_8);
|
||
|
|
GPIO_EXTI_IRQHandler(GPIO_Pin_9);
|
||
|
|
GPIO_EXTI_IRQHandler(GPIO_Pin_10);
|
||
|
|
GPIO_EXTI_IRQHandler(GPIO_Pin_11);
|
||
|
|
GPIO_EXTI_IRQHandler(GPIO_Pin_12);
|
||
|
|
GPIO_EXTI_IRQHandler(GPIO_Pin_13);
|
||
|
|
GPIO_EXTI_IRQHandler(GPIO_Pin_14);
|
||
|
|
GPIO_EXTI_IRQHandler(GPIO_Pin_15);
|
||
|
|
rt_interrupt_leave();
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
int rt_hw_pin_init(void)
|
||
|
|
{
|
||
|
|
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE);
|
||
|
|
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOB, ENABLE);
|
||
|
|
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOC, ENABLE);
|
||
|
|
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOD, ENABLE);
|
||
|
|
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOF, ENABLE);
|
||
|
|
return rt_device_pin_register("pin", &_ft32_pin_ops, RT_NULL);
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif /* RT_USING_PIN */
|