249 lines
7.3 KiB
C
249 lines
7.3 KiB
C
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/*
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* File : board.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006 - 2009 RT-Thread Develop Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Change Logs:
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* Date Author Notes
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* 2011-01-13 weety first version
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*/
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#include <rtthread.h>
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#include <rthw.h>
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#include "board.h"
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#include <mmu.h>
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/**
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* @addtogroup at91sam9g45
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*/
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/*@{*/
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#if defined(__CC_ARM)
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extern int Image$$ER_ZI$$ZI$$Limit;
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#define HEAP_BEGIN (&Image$$ER_ZI$$ZI$$Limit)
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#elif (defined (__GNUC__))
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extern unsigned char __bss_end__;
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#define HEAP_BEGIN (&__bss_end__)
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#elif (defined (__ICCARM__))
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#pragma section=".noinit"
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#define HEAP_BEGIN (__section_end(".noinit"))
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#endif
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#define HEAP_END (((rt_uint32_t)HEAP_BEGIN & 0xF0000000) + 0x04000000)
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extern void rt_hw_interrupt_init(void);
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extern void rt_hw_clock_init(void);
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extern void rt_hw_get_clock(void);
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extern void rt_hw_set_dividor(rt_uint8_t hdivn, rt_uint8_t pdivn);
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extern void rt_hw_set_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv);
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extern void rt_dbgu_isr(void);
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#define SAM9G45_BLOCK_SIZE 0x10000000 // 256M
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#define MMU_SECTION_SIZE 0x100000 // 1M
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#define PERIPHERALS_ADDR // 1M
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#define SECTION_END(sa) ((sa) + MMU_SECTION_SIZE - 1) // sa: start address
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#define BLOCK_END(ba) ((ba) + SAM9G45_BLOCK_SIZE - 1) // ba: block address
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static struct mem_desc at91_mem_desc[] = { /* FIXME, hornby, to confirm MMU and memory */
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{ 0x00000000, 0xFFFFFFFF , 0x00000000, RW_NCNB }, /* None cached for 4G memory */
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//{ 0x00000000, SECTION_END(0x00000000), 0x00000000, RW_CNB }, /* TLB for ITCM, ITCM map to address zero, 32KB */
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//{ 0x00200000, SECTION_END(0x00200000), 0x00200000, RW_CNB }, /* TLB for DTCM, 32KB */
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//{ 0x00300000, SECTION_END(0x00300000), 0x00300000, RW_CNB }, /* TLB for internal RAM, 64KB, we use it as global variable area */
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//{ 0x00600000, SECTION_END(0x00600000), 0x00600000, RW_NCNB }, /* TLB for UDPHS(DMA) */
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//{ 0x00700000, SECTION_END(0x00700000), 0x00700000, RW_NCNB }, /* TLB for UHP OHCI */
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//{ 0x00800000, SECTION_END(0x00800000), 0x00800000, RW_NCNB }, /* TLB for UHP EHCI */
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//{ 0x30000000, 0x30000000+0x00100000-1, 0x30000000, RW_CB }, /* 1M external SRAM for program code and stack */
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//{ 0x40000000, BLOCK_END(0x40000000), 0x40000000, RW_NCNB }, /* 256M for nand-flash controller */
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//{ 0x60000000, BLOCK_END(0x60000000), 0x60000000, RW_NCNB }, /* 256M for FPGA */
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//{ 0x70000000, 0x70000000+0x08000000-1, 0x70000000, RW_NCNB }, /* 128M for main DDR-SDRAM for print data */
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{ 0x00000000, SECTION_END(0x00000000), 0x70000000, RW_CB }, /* isr */
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{ 0x70000000, 0x70000000+0x08000000-1, 0x70000000, RW_CB }, /* 128M for main DDR-SDRAM for print data */
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//{ 0xFFF00000, SECTION_END(0xFFF00000), 0xFFF00000, RW_NCNB }, /* Internal Peripherals, 1MB */
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};
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#define PIT_CPIV(x) ((x) & AT91C_PITC_CPIV)
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#define PIT_PICNT(x) (((x) & AT91C_PITC_PICNT) >> 20)
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static rt_uint32_t pit_cycle; /* write-once */
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static rt_uint32_t pit_cnt; /* access only w/system irq blocked */
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/**
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* This function will handle rtos timer
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*/
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void rt_timer_handler(int vector, void *param)
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{
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#ifdef RT_USING_DBGU
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if (readl(AT91C_DBGU_CSR) & AT91C_US_RXRDY)
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{
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rt_dbgu_isr();
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}
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#endif
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if (readl(AT91C_PITC_PISR) & AT91C_PITC_PITS)
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{
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unsigned nr_ticks;
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/* Get number of ticks performed before irq, and ack it */
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nr_ticks = PIT_PICNT(readl(AT91C_PITC_PIVR));
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while (nr_ticks--)
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rt_tick_increase();
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}
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}
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static void at91sam9g45_pit_reset(void)
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{
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/* Disable timer and irqs */
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AT91C_BASE_PITC->PITC_PIMR = 0;
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/* Clear any pending interrupts, wait for PIT to stop counting */
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while (PIT_CPIV(readl(AT91C_PITC_PIVR)) != 0)
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;
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/* Start PIT but don't enable IRQ */
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//AT91C_BASE_PITC->PITC_PIMR = (pit_cycle - 1) | AT91C_PITC_PITEN;
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pit_cnt += pit_cycle * PIT_PICNT(readl(AT91C_PITC_PIVR));
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AT91C_BASE_PITC->PITC_PIMR =
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(pit_cycle - 1) | AT91C_PITC_PITEN | AT91C_PITC_PITIEN;
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rt_kprintf("PIT_MR=0x%08x\n", readl(AT91C_PITC_PIMR));
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}
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/*
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* Set up both clocksource and clockevent support.
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*/
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static void at91sam9g45_pit_init(void)
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{
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rt_uint32_t pit_rate;
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//rt_uint32_t bits;
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/*
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* Use our actual MCK to figure out how many MCK/16 ticks per
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* 1/HZ period (instead of a compile-time constant LATCH).
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*/
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pit_rate = clk_get_rate(clk_get("mck")) / 16;
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rt_kprintf("pit_rate=%dHZ\n", pit_rate);
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pit_cycle = (pit_rate + RT_TICK_PER_SECOND/2) / RT_TICK_PER_SECOND;
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/* Initialize and enable the timer */
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at91sam9g45_pit_reset();
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}
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/**
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* This function will init pit for system ticks
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*/
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void rt_hw_timer_init()
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{
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at91sam9g45_pit_init();
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/* install interrupt handler */
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rt_hw_interrupt_install(AT91C_ID_SYS, rt_timer_handler,
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RT_NULL, "system");
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rt_hw_interrupt_umask(AT91C_ID_SYS);
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}
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void at91_tc1_init()
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{
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AT91C_BASE_PMC->PMC_PCER = 1<<AT91C_ID_TC;
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writel(AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_NONE | AT91C_TCB_TC2XC2S_NONE, AT91C_TCB0_BMR);
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writel(AT91C_TC_CLKDIS, AT91C_TC0_CCR);
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writel(AT91C_TC_CLKS_TIMER_DIV4_CLOCK, AT91C_TC0_CMR);
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writel(0xffff, AT91C_TC0_CV);
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}
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#define BPS 115200 /* serial console port baudrate */
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static void at91_usart_putc(char c)
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{
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while (!(AT91C_BASE_DBGU->DBGU_CSR & AT91C_US_TXRDY))
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;
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AT91C_BASE_DBGU->DBGU_THR = c;
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}
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/**
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* This function is used to display a string on console, normally, it's
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* invoked by rt_kprintf
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*
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* @param str the displayed string
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*/
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void rt_hw_console_output(const char* str)
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{
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while (*str)
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{
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if (*str=='\n')
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{
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at91_usart_putc('\r');
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}
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at91_usart_putc(*str++);
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}
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}
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static void rt_hw_console_init(void)
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{
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int div;
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int mode = 0;
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AT91C_BASE_DBGU->DBGU_CR = AT91C_US_RSTTX | AT91C_US_RSTRX |
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AT91C_US_RXDIS | AT91C_US_TXDIS;
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mode |= AT91C_US_USMODE_NORMAL | AT91C_US_CLKS_CLOCK |
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AT91C_US_CHMODE_NORMAL;
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mode |= AT91C_US_CHRL_8_BITS;
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mode |= AT91C_US_NBSTOP_1_BIT;
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mode |= AT91C_US_PAR_NONE;
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AT91C_BASE_DBGU->DBGU_MR = mode;
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div = (clk_get_rate(clk_get("mck")) / 16 + BPS/2) / BPS;
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AT91C_BASE_DBGU->DBGU_BRGR = div;
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AT91C_BASE_DBGU->DBGU_CR = AT91C_US_RXEN | AT91C_US_TXEN;
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}
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/**
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* This function will init at91sam9g45 board
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*/
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void rt_hw_board_init()
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{
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/* initialize the system clock */
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rt_hw_clock_init();
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/* initialize console */
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rt_hw_console_init();
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/* initialize mmu */
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rt_hw_mmu_init(at91_mem_desc, sizeof(at91_mem_desc)/sizeof(at91_mem_desc[0]));
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/* initialize hardware interrupt */
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rt_hw_interrupt_init();
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/* initialize early device */
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#ifdef RT_USING_COMPONENTS_INIT
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rt_components_board_init();
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#endif
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#ifdef RT_USING_CONSOLE
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rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
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#endif
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/* initialize timer0 */
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rt_hw_timer_init();
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/* initialize board */
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#ifdef RT_USING_HEAP
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rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
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#endif
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}
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/*@}*/
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