423 lines
22 KiB
C
423 lines
22 KiB
C
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/*
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** ###################################################################
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** Processor: MK64FN1M0VMD12
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** Compilers: ARM Compiler
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** Freescale C/C++ for Embedded ARM
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** GNU C Compiler
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** GNU C Compiler - CodeSourcery Sourcery G++
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** IAR ANSI C/C++ Compiler for ARM
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**
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** Reference manual: K64P144M120SF5RM, Rev.1, July 2013
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** Version: rev. 2.1, 2013-10-29
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**
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** Abstract:
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** Provides a system configuration function and a global variable that
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** contains the system frequency. It configures the device and initializes
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** the oscillator (PLL) that is part of the microcontroller device.
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**
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** Copyright: 2013 Freescale, Inc. All Rights Reserved.
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**
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** http: www.freescale.com
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** mail: support@freescale.com
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**
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** Revisions:
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** - rev. 1.0 (2013-08-12)
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** Initial version.
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** - rev. 2.0 (2013-10-29)
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** Register accessor macros added to the memory map.
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** Symbols for Processor Expert memory map compatibility added to the memory map.
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** Startup file for gcc has been updated according to CMSIS 3.2.
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** System initialization updated.
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** MCG - registers updated.
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** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
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** - rev. 2.1 (2013-10-29)
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** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
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**
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** ###################################################################
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*/
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/*!
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* @file MK64F12
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* @version 2.1
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* @date 2013-10-29
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* @brief Device specific configuration file for MK64F12 (implementation file)
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*
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* Provides a system configuration function and a global variable that contains
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* the system frequency. It configures the device and initializes the oscillator
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* (PLL) that is part of the microcontroller device.
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*/
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#include <stdint.h>
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#include "MK64F12.h"
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#define DISABLE_WDOG 1
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#ifndef CLOCK_SETUP
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#define CLOCK_SETUP 4
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#endif
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/* Predefined clock setups
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0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
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Default part configuration.
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Reference clock source for MCG module is the slow internal clock source 32.768kHz
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Core clock = 20.97MHz, BusClock = 20.97MHz
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1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
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Maximum achievable clock frequency configuration.
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Reference clock source for MCG module is an external clock source 50MHz
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Core clock = 120MHz, BusClock = 60MHz
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2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power Internal (BLPI) mode
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Core clock/Bus clock derived directly from an fast internal clock 4MHz with no multiplication
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The clock settings is ready for Very Low Power Run mode.
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Core clock = 4MHz, BusClock = 4MHz
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3 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode
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Core clock/Bus clock derived directly from the RTC oscillator clock source 32.768kHz
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The clock settings is ready for Very Low Power Run mode.
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Core clock = 32.768kHz, BusClock = 32.768kHz
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4 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
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USB clock setup
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USB clock divider is set for USB to receive 48MHz input clock.
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Reference clock source for MCG module is an external clock source 50MHz
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USB clock divider is set for USB to receive 48MHz input clock.
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Core clock = 120MHz, BusClock = 60MHz
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*/
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/*----------------------------------------------------------------------------
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Define clock source values
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*----------------------------------------------------------------------------*/
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#if (CLOCK_SETUP == 0)
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#define CPU_XTAL_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */
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#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
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#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
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#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
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#define DEFAULT_SYSTEM_CLOCK 20485760u /* Default System clock value */
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#elif (CLOCK_SETUP == 1)
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#define CPU_XTAL_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */
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#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
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#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
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#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
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#define DEFAULT_SYSTEM_CLOCK 120000000u /* Default System clock value */
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#elif (CLOCK_SETUP == 2)
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#define CPU_XTAL_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */
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#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
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#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
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#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
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#define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */
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#elif (CLOCK_SETUP == 3)
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#define CPU_XTAL_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */
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#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
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#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
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#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
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#define DEFAULT_SYSTEM_CLOCK 32768u /* Default System clock value */
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#elif (CLOCK_SETUP == 4)
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#define CPU_XTAL_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */
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#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
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#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
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#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
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#define DEFAULT_SYSTEM_CLOCK 120000000u /* Default System clock value */
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#endif /* (CLOCK_SETUP == 4) */
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/* ----------------------------------------------------------------------------
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-- Core clock
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---------------------------------------------------------------------------- */
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uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
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/* ----------------------------------------------------------------------------
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-- SystemInit()
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---------------------------------------------------------------------------- */
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void SystemInit (void) {
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#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
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SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
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#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
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#if (DISABLE_WDOG)
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/* Disable the WDOG module */
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/* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
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WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
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/* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
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WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
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/* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
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WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
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WDOG_STCTRLH_WAITEN_MASK |
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WDOG_STCTRLH_STOPEN_MASK |
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WDOG_STCTRLH_ALLOWUPDATE_MASK |
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WDOG_STCTRLH_CLKSRC_MASK |
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0x0100U;
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#endif /* (DISABLE_WDOG) */
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/*
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* Release hold with ACKISO: Only has an effect if recovering from VLLSx.
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* if ACKISO is set you must clear ackiso before initializing the PLL
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* if osc enabled in low power modes - enable it first before ack
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*/
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if (PMC->REGSC & PMC_REGSC_ACKISO_MASK)
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{
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PMC->REGSC |= PMC_REGSC_ACKISO_MASK;
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}
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#if (CLOCK_SETUP == 0)
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/* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0 */
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SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) |
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SIM_CLKDIV1_OUTDIV2(0x00) |
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SIM_CLKDIV1_OUTDIV3(0x01) |
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SIM_CLKDIV1_OUTDIV4(0x01); /* Update system prescalers */
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/* SIM->SOPT2: PLLFLLSEL=0 */
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SIM->SOPT2 &= (uint32_t)~(uint32_t)(SIM_SOPT2_PLLFLLSEL_MASK); /* Select FLL as a clock source for various peripherals */
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/* SIM->SOPT1: OSC32KSEL=3 */
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SIM->SOPT1 |= SIM_SOPT1_OSC32KSEL(0x03); /* LPO 1kHz oscillator drives 32 kHz clock for various peripherals */
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/* Switch to FEI Mode */
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/* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
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MCG->C1 = MCG_C1_CLKS(0x00) |
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MCG_C1_FRDIV(0x00) |
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MCG_C1_IREFS_MASK |
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MCG_C1_IRCLKEN_MASK;
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/* MCG->C2: LOCRE0=0,?=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
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MCG->C2 = MCG_C2_RANGE0(0x00);
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/* MCG->C4: DMX32=0,DRST_DRS=0 */
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MCG->C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03)));
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/* OSC->CR: ERCLKEN=1,?=0,EREFSTEN=0,?=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
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OSC->CR = OSC_CR_ERCLKEN_MASK;
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/* MCG->C7: OSCSEL=0 */
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MCG->C7 &= (uint8_t)~(uint8_t)(MCG_C7_OSCSEL_MASK);
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/* MCG->C5: ?=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
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MCG->C5 = MCG_C5_PRDIV0(0x00);
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/* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
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MCG->C6 = MCG_C6_VDIV0(0x00);
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while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
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}
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while((MCG->S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */
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}
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#elif (CLOCK_SETUP == 1) || (CLOCK_SETUP == 4)
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/* SIM->SCGC5: PORTA=1 */
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SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK; /* Enable clock gate for ports to enable pin routing */
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/* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0 */
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SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) |
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SIM_CLKDIV1_OUTDIV2(0x01) |
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SIM_CLKDIV1_OUTDIV3(0x02) |
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SIM_CLKDIV1_OUTDIV4(0x04); /* Update system prescalers */
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/* SIM->SOPT2: PLLFLLSEL=1 */
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SIM->SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK; /* Select PLL as a clock source for various peripherals */
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/* SIM->SOPT1: OSC32KSEL=3 */
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SIM->SOPT1 |= SIM_SOPT1_OSC32KSEL(0x03); /* LPO 1kHz oscillator drives 32 kHz clock for various peripherals */
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/* PORTA->PCR[18]: ISF=0,MUX=0 */
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PORTA->PCR[18] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
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/* Switch to FBE Mode */
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/* MCG->C2: LOCRE0=0,?=0,RANGE0=2,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
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MCG->C2 = MCG_C2_RANGE0(0x02);
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/* OSC->CR: ERCLKEN=1,?=0,EREFSTEN=0,?=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
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OSC->CR = OSC_CR_ERCLKEN_MASK;
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/* MCG->C7: OSCSEL=0 */
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MCG->C7 &= (uint8_t)~(uint8_t)(MCG_C7_OSCSEL_MASK);
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/* MCG->C1: CLKS=2,FRDIV=5,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
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MCG->C1 = (MCG_C1_CLKS(0x02) | MCG_C1_FRDIV(0x07) | MCG_C1_IRCLKEN_MASK);
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/* MCG->C4: DMX32=0,DRST_DRS=0 */
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MCG->C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03)));
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/* MCG->C5: ?=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0x13 */
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MCG->C5 = MCG_C5_PRDIV0(0x13);
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/* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0x18 */
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MCG->C6 = MCG_C6_VDIV0(0x18);
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while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
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}
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while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
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}
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/* Switch to PBE Mode */
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/* MCG->C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0x18 */
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MCG->C6 = (MCG_C6_PLLS_MASK | MCG_C6_VDIV0(0x18));
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while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
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}
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while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until locked */
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}
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/* Switch to PEE Mode */
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/* MCG->C1: CLKS=0,FRDIV=5,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
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MCG->C1 = (MCG_C1_CLKS(0x00) | MCG_C1_FRDIV(0x05) | MCG_C1_IRCLKEN_MASK);
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while((MCG->S & 0x0CU) != 0x0CU) { /* Wait until output of the PLL is selected */
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}
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#if (CLOCK_SETUP == 4)
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/* Set USB input clock to 48MHz */
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/* SIM->CLKDIV2: USBDIV=4,USBFRAC=1 */
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SIM->CLKDIV2 = (uint32_t)((SIM->CLKDIV2 & (uint32_t)~(uint32_t)(
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SIM_CLKDIV2_USBDIV(0x03)
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)) | (uint32_t)(
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SIM_CLKDIV2_USBDIV(0x04) |
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SIM_CLKDIV2_USBFRAC_MASK
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));
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#endif
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#elif (CLOCK_SETUP == 2)
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/* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=4,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0 */
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SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) |
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SIM_CLKDIV1_OUTDIV2(0x00) |
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SIM_CLKDIV1_OUTDIV3(0x00) |
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SIM_CLKDIV1_OUTDIV4(0x04); /* Update system prescalers */
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/* SIM->SOPT2: PLLFLLSEL=0 */
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SIM->SOPT2 &= (uint32_t)~(uint32_t)(SIM_SOPT2_PLLFLLSEL_MASK); /* Select FLL as a clock source for various peripherals */
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/* SIM->SOPT1: OSC32KSEL=3 */
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SIM->SOPT1 |= SIM_SOPT1_OSC32KSEL(0x03); /* LPO 1kHz oscillator drives 32 kHz clock for various peripherals */
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/* MCG->SC: FCRDIV=0 */
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MCG->SC &= (uint8_t)~(uint8_t)(MCG_SC_FCRDIV(0x07));
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/* Switch to FBI Mode */
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/* MCG->C1: CLKS=1,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
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MCG->C1 = MCG_C1_CLKS(0x01) |
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MCG_C1_FRDIV(0x00) |
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MCG_C1_IREFS_MASK |
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MCG_C1_IRCLKEN_MASK;
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|
/* MCG->C2: LOCRE0=0,?=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=1 */
|
||
|
|
MCG->C2 = (MCG_C2_RANGE0(0x00) | MCG_C2_IRCS_MASK);
|
||
|
|
/* MCG->C4: DMX32=0,DRST_DRS=0 */
|
||
|
|
MCG->C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03)));
|
||
|
|
/* OSC->CR: ERCLKEN=1,?=0,EREFSTEN=0,?=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
|
||
|
|
OSC->CR = OSC_CR_ERCLKEN_MASK;
|
||
|
|
/* MCG->C7: OSCSEL=0 */
|
||
|
|
MCG->C7 &= (uint8_t)~(uint8_t)(MCG_C7_OSCSEL_MASK);
|
||
|
|
/* MCG->C5: ?=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
|
||
|
|
MCG->C5 = MCG_C5_PRDIV0(0x00);
|
||
|
|
/* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
|
||
|
|
MCG->C6 = MCG_C6_VDIV0(0x00);
|
||
|
|
while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
|
||
|
|
}
|
||
|
|
while((MCG->S & 0x0CU) != 0x04U) { /* Wait until internal reference clock is selected as MCG output */
|
||
|
|
}
|
||
|
|
/* Switch to BLPI Mode */
|
||
|
|
/* MCG->C2: LOCRE0=0,?=0,RANGE0=0,HGO0=0,EREFS0=0,LP=1,IRCS=1 */
|
||
|
|
MCG->C2 = (MCG_C2_RANGE0(0x00) | MCG_C2_LP_MASK | MCG_C2_IRCS_MASK);
|
||
|
|
while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
|
||
|
|
}
|
||
|
|
while((MCG->S & MCG_S_IRCST_MASK) == 0x00U) { /* Check that the fast external reference clock is selected. */
|
||
|
|
}
|
||
|
|
#elif (CLOCK_SETUP == 3)
|
||
|
|
/* SIM->SCGC6: RTC=1 */
|
||
|
|
SIM->SCGC6 |= SIM_SCGC6_RTC_MASK;
|
||
|
|
if ((RTC->CR & RTC_CR_OSCE_MASK) == 0u) { /* Only if the OSCILLATOR is not already enabled */
|
||
|
|
/* RTC->CR: SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
|
||
|
|
RTC->CR &= (uint32_t)~(uint32_t)(
|
||
|
|
RTC_CR_SC2P_MASK |
|
||
|
|
RTC_CR_SC4P_MASK |
|
||
|
|
RTC_CR_SC8P_MASK |
|
||
|
|
RTC_CR_SC16P_MASK
|
||
|
|
);
|
||
|
|
/* RTC->CR: OSCE=1 */
|
||
|
|
RTC->CR |= RTC_CR_OSCE_MASK;
|
||
|
|
/* RTC->CR: CLKO=0 */
|
||
|
|
RTC->CR &= (uint32_t)~(uint32_t)(RTC_CR_CLKO_MASK);
|
||
|
|
}
|
||
|
|
/* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0,?=0 */
|
||
|
|
SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) |
|
||
|
|
SIM_CLKDIV1_OUTDIV2(0x00) |
|
||
|
|
SIM_CLKDIV1_OUTDIV3(0x00) |
|
||
|
|
SIM_CLKDIV1_OUTDIV4(0x00); /* Update system prescalers */
|
||
|
|
/* SIM->SOPT1: OSC32KSEL=2 */
|
||
|
|
SIM->SOPT1 = (uint32_t)((SIM->SOPT1 & (uint32_t)~(uint32_t)(
|
||
|
|
SIM_SOPT1_OSC32KSEL(0x01)
|
||
|
|
)) | (uint32_t)(
|
||
|
|
SIM_SOPT1_OSC32KSEL(0x02)
|
||
|
|
)); /* System oscillator drives 32 kHz clock for various peripherals */
|
||
|
|
/* Switch to FBE Mode */
|
||
|
|
/* MCG->C2: LOCRE0=0,?=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
|
||
|
|
MCG->C2 = MCG_C2_RANGE0(0x00);
|
||
|
|
/* OSC->CR: ERCLKEN=1,?=0,EREFSTEN=0,?=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
|
||
|
|
OSC->CR = OSC_CR_ERCLKEN_MASK;
|
||
|
|
/* MCG->C7: OSCSEL=1 */
|
||
|
|
MCG->C7 |= MCG_C7_OSCSEL_MASK;
|
||
|
|
/* MCG->C1: CLKS=2,FRDIV=0,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
|
||
|
|
MCG->C1 = (MCG_C1_CLKS(0x02) | MCG_C1_FRDIV(0x00) | MCG_C1_IRCLKEN_MASK);
|
||
|
|
/* MCG->C4: DMX32=0,DRST_DRS=0 */
|
||
|
|
MCG->C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03)));
|
||
|
|
/* MCG->C5: ?=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
|
||
|
|
MCG->C5 = MCG_C5_PRDIV0(0x00);
|
||
|
|
/* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
|
||
|
|
MCG->C6 = MCG_C6_VDIV0(0x00);
|
||
|
|
while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
|
||
|
|
}
|
||
|
|
while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
|
||
|
|
}
|
||
|
|
/* Switch to BLPE Mode */
|
||
|
|
/* MCG->C2: LOCRE0=0,?=0,RANGE0=0,HGO0=0,EREFS0=0,LP=1,IRCS=0 */
|
||
|
|
MCG->C2 = (MCG_C2_RANGE0(0x00) | MCG_C2_LP_MASK);
|
||
|
|
while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
/* ----------------------------------------------------------------------------
|
||
|
|
-- SystemCoreClockUpdate()
|
||
|
|
---------------------------------------------------------------------------- */
|
||
|
|
|
||
|
|
void SystemCoreClockUpdate (void) {
|
||
|
|
uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
|
||
|
|
uint8_t Divider;
|
||
|
|
|
||
|
|
if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) {
|
||
|
|
/* Output of FLL or PLL is selected */
|
||
|
|
if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) {
|
||
|
|
/* FLL is selected */
|
||
|
|
if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) {
|
||
|
|
/* External reference clock is selected */
|
||
|
|
if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) {
|
||
|
|
MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
|
||
|
|
} else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
|
||
|
|
MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
|
||
|
|
} /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
|
||
|
|
Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
|
||
|
|
MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
|
||
|
|
if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) {
|
||
|
|
MCGOUTClock /= 32u; /* If high range is enabled, additional 32 divider is active */
|
||
|
|
} /* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) */
|
||
|
|
} else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
|
||
|
|
MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
|
||
|
|
} /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
|
||
|
|
/* Select correct multiplier to calculate the MCG output clock */
|
||
|
|
switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
|
||
|
|
case 0x0u:
|
||
|
|
MCGOUTClock *= 640u;
|
||
|
|
break;
|
||
|
|
case 0x20u:
|
||
|
|
MCGOUTClock *= 1280u;
|
||
|
|
break;
|
||
|
|
case 0x40u:
|
||
|
|
MCGOUTClock *= 1920u;
|
||
|
|
break;
|
||
|
|
case 0x60u:
|
||
|
|
MCGOUTClock *= 2560u;
|
||
|
|
break;
|
||
|
|
case 0x80u:
|
||
|
|
MCGOUTClock *= 732u;
|
||
|
|
break;
|
||
|
|
case 0xA0u:
|
||
|
|
MCGOUTClock *= 1464u;
|
||
|
|
break;
|
||
|
|
case 0xC0u:
|
||
|
|
MCGOUTClock *= 2197u;
|
||
|
|
break;
|
||
|
|
case 0xE0u:
|
||
|
|
MCGOUTClock *= 2929u;
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
} else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
|
||
|
|
/* PLL is selected */
|
||
|
|
Divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
|
||
|
|
MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
|
||
|
|
Divider = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u);
|
||
|
|
MCGOUTClock *= Divider; /* Calculate the MCG output clock */
|
||
|
|
} /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
|
||
|
|
} else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) {
|
||
|
|
/* Internal reference clock is selected */
|
||
|
|
if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) {
|
||
|
|
MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
|
||
|
|
} else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
|
||
|
|
MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); /* Fast internal reference clock selected */
|
||
|
|
} /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
|
||
|
|
} else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) {
|
||
|
|
/* External reference clock is selected */
|
||
|
|
if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) {
|
||
|
|
MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
|
||
|
|
} else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
|
||
|
|
MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
|
||
|
|
} /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
|
||
|
|
} else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
|
||
|
|
/* Reserved value */
|
||
|
|
return;
|
||
|
|
} /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
|
||
|
|
SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
|
||
|
|
}
|