303 lines
10 KiB
C
303 lines
10 KiB
C
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/*
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* Copyright (c) 2014, Freescale Semiconductor, Inc.
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* All rights reserved.
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*
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* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
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* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
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* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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* OF SUCH DAMAGE.
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*/
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/*
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* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
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*
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* This file was generated automatically and any changes may be lost.
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*/
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#ifndef __HW_OSC_REGISTERS_H__
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#define __HW_OSC_REGISTERS_H__
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#include "regs.h"
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/*
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* MK64F12 OSC
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*
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* Oscillator
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*
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* Registers defined in this header file:
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* - HW_OSC_CR - OSC Control Register
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*
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* - hw_osc_t - Struct containing all module registers.
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*/
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//! @name Module base addresses
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//@{
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#ifndef REGS_OSC_BASE
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#define HW_OSC_INSTANCE_COUNT (1U) //!< Number of instances of the OSC module.
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#define HW_OSC0 (0U) //!< Instance number for OSC.
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#define REGS_OSC0_BASE (0x40065000U) //!< Base address for OSC.
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//! @brief Table of base addresses for OSC instances.
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static const uint32_t __g_regs_OSC_base_addresses[] = {
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REGS_OSC0_BASE,
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};
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//! @brief Get the base address of OSC by instance number.
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//! @param x OSC instance number, from 0 through 0.
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#define REGS_OSC_BASE(x) (__g_regs_OSC_base_addresses[(x)])
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//! @brief Get the instance number given a base address.
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//! @param b Base address for an instance of OSC.
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#define REGS_OSC_INSTANCE(b) ((b) == REGS_OSC0_BASE ? HW_OSC0 : 0)
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_OSC_CR - OSC Control Register
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
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* @brief HW_OSC_CR - OSC Control Register (RW)
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*
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* Reset value: 0x00U
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*
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* After OSC is enabled and starts generating the clocks, the configurations
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* such as low power and frequency range, must not be changed.
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*/
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typedef union _hw_osc_cr
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{
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uint8_t U;
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struct _hw_osc_cr_bitfields
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{
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uint8_t SC16P : 1; //!< [0] Oscillator 16 pF Capacitor Load Configure
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uint8_t SC8P : 1; //!< [1] Oscillator 8 pF Capacitor Load Configure
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uint8_t SC4P : 1; //!< [2] Oscillator 4 pF Capacitor Load Configure
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uint8_t SC2P : 1; //!< [3] Oscillator 2 pF Capacitor Load Configure
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uint8_t RESERVED0 : 1; //!< [4]
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uint8_t EREFSTEN : 1; //!< [5] External Reference Stop Enable
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uint8_t RESERVED1 : 1; //!< [6]
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uint8_t ERCLKEN : 1; //!< [7] External Reference Enable
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} B;
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} hw_osc_cr_t;
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#endif
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/*!
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* @name Constants and macros for entire OSC_CR register
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*/
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//@{
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#define HW_OSC_CR_ADDR(x) (REGS_OSC_BASE(x) + 0x0U)
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#ifndef __LANGUAGE_ASM__
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#define HW_OSC_CR(x) (*(__IO hw_osc_cr_t *) HW_OSC_CR_ADDR(x))
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#define HW_OSC_CR_RD(x) (HW_OSC_CR(x).U)
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#define HW_OSC_CR_WR(x, v) (HW_OSC_CR(x).U = (v))
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#define HW_OSC_CR_SET(x, v) (HW_OSC_CR_WR(x, HW_OSC_CR_RD(x) | (v)))
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#define HW_OSC_CR_CLR(x, v) (HW_OSC_CR_WR(x, HW_OSC_CR_RD(x) & ~(v)))
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#define HW_OSC_CR_TOG(x, v) (HW_OSC_CR_WR(x, HW_OSC_CR_RD(x) ^ (v)))
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#endif
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//@}
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/*
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* Constants & macros for individual OSC_CR bitfields
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*/
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/*!
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* @name Register OSC_CR, field SC16P[0] (RW)
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*
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* Configures the oscillator load.
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*
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* Values:
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* - 0 - Disable the selection.
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* - 1 - Add 16 pF capacitor to the oscillator load.
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*/
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//@{
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#define BP_OSC_CR_SC16P (0U) //!< Bit position for OSC_CR_SC16P.
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#define BM_OSC_CR_SC16P (0x01U) //!< Bit mask for OSC_CR_SC16P.
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#define BS_OSC_CR_SC16P (1U) //!< Bit field size in bits for OSC_CR_SC16P.
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#ifndef __LANGUAGE_ASM__
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//! @brief Read current value of the OSC_CR_SC16P field.
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#define BR_OSC_CR_SC16P(x) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC16P))
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#endif
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//! @brief Format value for bitfield OSC_CR_SC16P.
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#define BF_OSC_CR_SC16P(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_OSC_CR_SC16P), uint8_t) & BM_OSC_CR_SC16P)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the SC16P field to a new value.
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#define BW_OSC_CR_SC16P(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC16P) = (v))
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#endif
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//@}
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/*!
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* @name Register OSC_CR, field SC8P[1] (RW)
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*
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* Configures the oscillator load.
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*
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* Values:
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* - 0 - Disable the selection.
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* - 1 - Add 8 pF capacitor to the oscillator load.
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*/
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//@{
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#define BP_OSC_CR_SC8P (1U) //!< Bit position for OSC_CR_SC8P.
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#define BM_OSC_CR_SC8P (0x02U) //!< Bit mask for OSC_CR_SC8P.
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#define BS_OSC_CR_SC8P (1U) //!< Bit field size in bits for OSC_CR_SC8P.
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#ifndef __LANGUAGE_ASM__
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//! @brief Read current value of the OSC_CR_SC8P field.
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#define BR_OSC_CR_SC8P(x) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC8P))
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#endif
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//! @brief Format value for bitfield OSC_CR_SC8P.
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#define BF_OSC_CR_SC8P(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_OSC_CR_SC8P), uint8_t) & BM_OSC_CR_SC8P)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the SC8P field to a new value.
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#define BW_OSC_CR_SC8P(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC8P) = (v))
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#endif
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//@}
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/*!
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* @name Register OSC_CR, field SC4P[2] (RW)
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*
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* Configures the oscillator load.
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*
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* Values:
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* - 0 - Disable the selection.
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* - 1 - Add 4 pF capacitor to the oscillator load.
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*/
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//@{
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#define BP_OSC_CR_SC4P (2U) //!< Bit position for OSC_CR_SC4P.
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#define BM_OSC_CR_SC4P (0x04U) //!< Bit mask for OSC_CR_SC4P.
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#define BS_OSC_CR_SC4P (1U) //!< Bit field size in bits for OSC_CR_SC4P.
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#ifndef __LANGUAGE_ASM__
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//! @brief Read current value of the OSC_CR_SC4P field.
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#define BR_OSC_CR_SC4P(x) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC4P))
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#endif
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//! @brief Format value for bitfield OSC_CR_SC4P.
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#define BF_OSC_CR_SC4P(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_OSC_CR_SC4P), uint8_t) & BM_OSC_CR_SC4P)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the SC4P field to a new value.
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#define BW_OSC_CR_SC4P(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC4P) = (v))
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#endif
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//@}
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/*!
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* @name Register OSC_CR, field SC2P[3] (RW)
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*
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* Configures the oscillator load.
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*
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* Values:
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* - 0 - Disable the selection.
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* - 1 - Add 2 pF capacitor to the oscillator load.
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*/
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//@{
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#define BP_OSC_CR_SC2P (3U) //!< Bit position for OSC_CR_SC2P.
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#define BM_OSC_CR_SC2P (0x08U) //!< Bit mask for OSC_CR_SC2P.
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#define BS_OSC_CR_SC2P (1U) //!< Bit field size in bits for OSC_CR_SC2P.
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#ifndef __LANGUAGE_ASM__
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//! @brief Read current value of the OSC_CR_SC2P field.
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#define BR_OSC_CR_SC2P(x) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC2P))
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#endif
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//! @brief Format value for bitfield OSC_CR_SC2P.
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#define BF_OSC_CR_SC2P(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_OSC_CR_SC2P), uint8_t) & BM_OSC_CR_SC2P)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the SC2P field to a new value.
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#define BW_OSC_CR_SC2P(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC2P) = (v))
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#endif
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//@}
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/*!
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* @name Register OSC_CR, field EREFSTEN[5] (RW)
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*
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* Controls whether or not the external reference clock (OSCERCLK) remains
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* enabled when MCU enters Stop mode.
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*
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* Values:
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* - 0 - External reference clock is disabled in Stop mode.
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* - 1 - External reference clock stays enabled in Stop mode if ERCLKEN is set
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* before entering Stop mode.
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*/
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//@{
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#define BP_OSC_CR_EREFSTEN (5U) //!< Bit position for OSC_CR_EREFSTEN.
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#define BM_OSC_CR_EREFSTEN (0x20U) //!< Bit mask for OSC_CR_EREFSTEN.
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#define BS_OSC_CR_EREFSTEN (1U) //!< Bit field size in bits for OSC_CR_EREFSTEN.
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#ifndef __LANGUAGE_ASM__
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//! @brief Read current value of the OSC_CR_EREFSTEN field.
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#define BR_OSC_CR_EREFSTEN(x) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_EREFSTEN))
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#endif
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//! @brief Format value for bitfield OSC_CR_EREFSTEN.
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#define BF_OSC_CR_EREFSTEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_OSC_CR_EREFSTEN), uint8_t) & BM_OSC_CR_EREFSTEN)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the EREFSTEN field to a new value.
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#define BW_OSC_CR_EREFSTEN(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_EREFSTEN) = (v))
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#endif
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//@}
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/*!
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* @name Register OSC_CR, field ERCLKEN[7] (RW)
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*
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* Enables external reference clock (OSCERCLK).
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*
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* Values:
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* - 0 - External reference clock is inactive.
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* - 1 - External reference clock is enabled.
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*/
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//@{
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#define BP_OSC_CR_ERCLKEN (7U) //!< Bit position for OSC_CR_ERCLKEN.
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#define BM_OSC_CR_ERCLKEN (0x80U) //!< Bit mask for OSC_CR_ERCLKEN.
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#define BS_OSC_CR_ERCLKEN (1U) //!< Bit field size in bits for OSC_CR_ERCLKEN.
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#ifndef __LANGUAGE_ASM__
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//! @brief Read current value of the OSC_CR_ERCLKEN field.
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#define BR_OSC_CR_ERCLKEN(x) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_ERCLKEN))
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#endif
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//! @brief Format value for bitfield OSC_CR_ERCLKEN.
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#define BF_OSC_CR_ERCLKEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_OSC_CR_ERCLKEN), uint8_t) & BM_OSC_CR_ERCLKEN)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the ERCLKEN field to a new value.
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#define BW_OSC_CR_ERCLKEN(x, v) (BITBAND_ACCESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_ERCLKEN) = (v))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// hw_osc_t - module struct
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//-------------------------------------------------------------------------------------------
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/*!
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* @brief All OSC module registers.
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*/
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#ifndef __LANGUAGE_ASM__
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#pragma pack(1)
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typedef struct _hw_osc
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{
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__IO hw_osc_cr_t CR; //!< [0x0] OSC Control Register
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} hw_osc_t;
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#pragma pack()
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//! @brief Macro to access all OSC registers.
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//! @param x OSC instance number.
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//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
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//! use the '&' operator, like <code>&HW_OSC(0)</code>.
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#define HW_OSC(x) (*(hw_osc_t *) REGS_OSC_BASE(x))
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#endif
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#endif // __HW_OSC_REGISTERS_H__
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// v22/130726/0.9
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// EOF
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