127 lines
7.4 KiB
C
127 lines
7.4 KiB
C
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/*!
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\file gd32vf103_exmc.h
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\brief definitions for the EXMC
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\version 2019-6-5, V1.0.0, firmware for GD32VF103
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*/
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/*
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Copyright (c) 2019, GigaDevice Semiconductor Inc.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#ifndef GD32VF103_EXMC_H
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#define GD32VF103_EXMC_H
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#include "gd32vf103.h"
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/* EXMC definitions */
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#define EXMC (EXMC_BASE) /*!< EXMC register base address */
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/* registers definitions */
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/* NOR/PSRAM */
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#define EXMC_SNCTL0 REG32(EXMC + 0x00U) /*!< EXMC SRAM/NOR flash control register 0 */
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#define EXMC_SNTCFG0 REG32(EXMC + 0x04U) /*!< EXMC SRAM/NOR flash timing configuration register 0 */
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#define EXMC_SNWTCFG0 REG32(EXMC + 0x104U) /*!< EXMC SRAM/NOR flash write timing configuration register 0 */
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/* bits definitions */
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/* NOR/PSRAM */
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/* EXMC_SNCTLx, x=0 */
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#define EXMC_SNCTL_NRBKEN BIT(0) /*!< NOR bank enable */
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#define EXMC_SNCTL_NRMUX BIT(1) /*!< NOR bank memory address/data multiplexing */
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#define EXMC_SNCTL_NRTP BITS(2,3) /*!< NOR bank memory type */
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#define EXMC_SNCTL_NRW BITS(4,5) /*!< NOR bank memory data bus width */
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#define EXMC_SNCTL_NREN BIT(6) /*!< NOR flash access enable */
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#define EXMC_SNCTL_NRWTPOL BIT(9) /*!< NWAIT signal polarity */
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#define EXMC_SNCTL_WREN BIT(12) /*!< write enable */
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#define EXMC_SNCTL_NRWTEN BIT(13) /*!< NWAIT signal enable */
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#define EXMC_SNCTL_ASYNCWAIT BIT(15) /*!< asynchronous wait */
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/* EXMC_SNTCFGx, x=0 */
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#define EXMC_SNTCFG_ASET BITS(0,3) /*!< address setup time */
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#define EXMC_SNTCFG_AHLD BITS(4,7) /*!< address hold time */
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#define EXMC_SNTCFG_DSET BITS(8,15) /*!< data setup time */
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#define EXMC_SNTCFG_BUSLAT BITS(16,19) /*!< bus latency */
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/* constants definitions */
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/* EXMC NOR/SRAM timing initialize struct */
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typedef struct
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{
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uint32_t bus_latency; /*!< configure the bus latency */
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uint32_t asyn_data_setuptime; /*!< configure the data setup time,asynchronous access mode valid */
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uint32_t asyn_address_holdtime; /*!< configure the address hold time,asynchronous access mode valid */
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uint32_t asyn_address_setuptime; /*!< configure the data setup time,asynchronous access mode valid */
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}exmc_norsram_timing_parameter_struct;
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/* EXMC NOR/SRAM initialize struct */
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typedef struct
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{
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uint32_t norsram_region; /*!< select the region of EXMC NOR/SRAM bank */
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uint32_t asyn_wait; /*!< enable or disable the asynchronous wait function */
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uint32_t nwait_signal; /*!< enable or disable the NWAIT signal */
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uint32_t memory_write; /*!< enable or disable the write operation */
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uint32_t nwait_polarity; /*!< specifies the polarity of NWAIT signal from memory */
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uint32_t databus_width; /*!< specifies the databus width of external memory */
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uint32_t memory_type; /*!< specifies the type of external memory */
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uint32_t address_data_mux; /*!< specifies whether the data bus and address bus are multiplexed */
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exmc_norsram_timing_parameter_struct* read_write_timing; /*!< timing parameters for read and write */
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}exmc_norsram_parameter_struct;
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/* EXMC register address */
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#define EXMC_SNCTL(region) REG32(EXMC + 0x08U * (region)) /*!< EXMC SRAM/NOR flash control register */
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#define EXMC_SNTCFG(region) REG32(EXMC + 0x04U + 0x08U * (region)) /*!< EXMC SRAM/NOR flash timing configuration register */
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/* NOR bank memory data bus width */
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#define SNCTL_NRW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4))
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#define EXMC_NOR_DATABUS_WIDTH_8B SNCTL_NRW(0) /*!< NOR data width 8 bits */
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#define EXMC_NOR_DATABUS_WIDTH_16B SNCTL_NRW(1) /*!< NOR data width 16 bits */
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/* NOR bank memory type */
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#define SNCTL_NRTP(regval) (BITS(2,3) & ((uint32_t)(regval) << 2))
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#define EXMC_MEMORY_TYPE_SRAM SNCTL_NRTP(0) /*!< SRAM,ROM */
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#define EXMC_MEMORY_TYPE_PSRAM SNCTL_NRTP(1) /*!< PSRAM,CRAM */
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#define EXMC_MEMORY_TYPE_NOR SNCTL_NRTP(2) /*!< NOR flash */
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/* EXMC NOR/SRAM bank region definition */
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#define EXMC_BANK0_NORSRAM_REGION0 ((uint32_t)0x00000000U) /*!< bank0 NOR/SRAM region0 */
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/* EXMC NWAIT signal polarity configuration */
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#define EXMC_NWAIT_POLARITY_LOW ((uint32_t)0x00000000U) /*!< low level is active of NWAIT */
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#define EXMC_NWAIT_POLARITY_HIGH ((uint32_t)0x00000200U) /*!< high level is active of NWAIT */
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/* function declarations */
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/* deinitialize EXMC NOR/SRAM region */
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void exmc_norsram_deinit(uint32_t norsram_region);
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/* exmc_norsram_parameter_struct parameter initialize */
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void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct);
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/* initialize EXMC NOR/SRAM region */
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void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct);
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/* EXMC NOR/SRAM bank enable */
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void exmc_norsram_enable(uint32_t norsram_region);
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/* EXMC NOR/SRAM bank disable */
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void exmc_norsram_disable(uint32_t norsram_region);
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#endif /* GD32VF103_EXMC_H */
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