2019-03-27 16:49:26 +08:00
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/*
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2019-03-29 10:50:01 +08:00
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* Copyright (c) 2019 Winner Microelectronics Co., Ltd.
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2019-03-27 16:49:26 +08:00
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018-09-15 flyingcys 1st version
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*/
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#include <rtthread.h>
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#include <rtdevice.h>
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#include <rthw.h>
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#include "wm_type_def.h"
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#include "wm_io.h"
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#include "wm_gpio.h"
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#include "pin_map.h"
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#include "drv_pin.h"
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#ifdef BSP_USING_PIN
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static void wm_pin_mode(struct rt_device *device, rt_base_t pin, rt_base_t mode)
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{
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rt_int16_t gpio_pin;
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gpio_pin = wm_get_pin(pin);
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if (gpio_pin < 0)
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{
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return;
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}
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if (mode == PIN_MODE_INPUT)
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{
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tls_gpio_cfg((enum tls_io_name)gpio_pin, WM_GPIO_DIR_INPUT, WM_GPIO_ATTR_FLOATING);
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}
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else if (mode == PIN_MODE_INPUT_PULLUP)
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{
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tls_gpio_cfg((enum tls_io_name)gpio_pin, WM_GPIO_DIR_INPUT, WM_GPIO_ATTR_PULLHIGH);
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}
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else if (mode == PIN_MODE_INPUT_PULLDOWN)
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{
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tls_gpio_cfg((enum tls_io_name)gpio_pin, WM_GPIO_DIR_INPUT, WM_GPIO_ATTR_PULLLOW);
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}
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else if (mode == PIN_MODE_OUTPUT)
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{
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tls_gpio_cfg((enum tls_io_name)gpio_pin, WM_GPIO_DIR_OUTPUT, WM_GPIO_ATTR_PULLHIGH);
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}
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return;
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}
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static void wm_pin_write(struct rt_device *device, rt_base_t pin, rt_base_t value)
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{
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rt_int16_t gpio_pin;
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gpio_pin = wm_get_pin(pin);
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if (gpio_pin < 0)
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{
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return;
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}
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tls_gpio_write((enum tls_io_name)gpio_pin, value);
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return;
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}
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static int wm_pin_read(struct rt_device *device, rt_base_t pin)
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{
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rt_int16_t gpio_pin;
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gpio_pin = wm_get_pin(pin);
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if (gpio_pin < 0)
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{
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return PIN_LOW;
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}
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return tls_gpio_read((enum tls_io_name)gpio_pin);
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}
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static rt_err_t wm_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
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rt_uint32_t mode, void (*hdr)(void *args), void *args)
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{
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rt_int16_t gpio_pin;
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rt_base_t level;
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gpio_pin = wm_get_pin(pin);
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if (gpio_pin < 0)
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{
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return RT_ENOSYS;
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}
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level = rt_hw_interrupt_disable();
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/*irq mode set*/
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switch (mode)
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{
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case PIN_IRQ_MODE_RISING:
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tls_gpio_irq_cfg((enum tls_io_name)gpio_pin, WM_GPIO_IRQ_TRIG_RISING_EDGE);
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break;
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case PIN_IRQ_MODE_FALLING:
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tls_gpio_irq_cfg((enum tls_io_name)gpio_pin, WM_GPIO_IRQ_TRIG_FALLING_EDGE);
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break;
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case PIN_IRQ_MODE_RISING_FALLING:
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tls_gpio_irq_cfg((enum tls_io_name)gpio_pin, WM_GPIO_IRQ_TRIG_DOUBLE_EDGE);
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break;
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case PIN_IRQ_MODE_HIGH_LEVEL:
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tls_gpio_irq_cfg((enum tls_io_name)gpio_pin, WM_GPIO_IRQ_TRIG_HIGH_LEVEL);
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break;
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case PIN_IRQ_MODE_LOW_LEVEL:
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tls_gpio_irq_cfg((enum tls_io_name)gpio_pin, WM_GPIO_IRQ_TRIG_LOW_LEVEL);
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break;
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default:
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rt_hw_interrupt_enable(level);
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return RT_ENOSYS;
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}
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tls_gpio_isr_register((enum tls_io_name)gpio_pin, hdr, args);
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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static rt_err_t wm_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
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{
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return RT_EOK;
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}
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static rt_err_t wm_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
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{
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rt_int16_t gpio_pin;
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rt_base_t level;
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gpio_pin = wm_get_pin(pin);
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if (gpio_pin < 0)
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{
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return RT_ENOSYS;
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}
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level = rt_hw_interrupt_disable();
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if (enabled == PIN_IRQ_ENABLE)
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{
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tls_clr_gpio_irq_status((enum tls_io_name)gpio_pin);
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tls_gpio_irq_enable((enum tls_io_name)gpio_pin);
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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else if (enabled == PIN_IRQ_DISABLE)
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{
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tls_gpio_irq_disable((enum tls_io_name)gpio_pin);
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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else
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{
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rt_hw_interrupt_enable(level);
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return RT_ENOSYS;
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}
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}
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struct rt_pin_ops _wm_pin_ops =
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{
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wm_pin_mode,
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wm_pin_write,
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wm_pin_read,
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wm_pin_attach_irq,
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wm_pin_detach_irq,
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wm_pin_irq_enable
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};
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int wm_hw_pin_init(void)
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{
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int ret = rt_device_pin_register("pin", &_wm_pin_ops, RT_NULL);
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return ret;
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}
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INIT_BOARD_EXPORT(wm_hw_pin_init);
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void WM_GPIOA_IRQHandler(void)
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{
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rt_interrupt_enter();
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GPIOA_IRQHandler();
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rt_interrupt_leave();
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}
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void WM_GPIOB_IRQHandler(void)
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{
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rt_interrupt_enter();
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GPIOB_IRQHandler();
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rt_interrupt_leave();
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}
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#endif /* BSP_USING_PIN */
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