2013-01-08 22:40:58 +08:00
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/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
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/*This file has been prepared for Doxygen automatic documentation generation.*/
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/*! \file *********************************************************************
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*
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* \brief Power Manager driver.
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*
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*
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* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
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* - Supported devices: All AVR32 devices.
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* - AppNote:
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*
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* \author Atmel Corporation: http://www.atmel.com \n
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* Support and FAQ: http://support.atmel.no/
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*
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*****************************************************************************/
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/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of Atmel may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* 4. This software may only be redistributed and used in connection with an Atmel
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* AVR product.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
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*
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*/
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#ifndef _PM_H_
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#define _PM_H_
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#include <avr32/io.h>
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#include "compiler.h"
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#include "preprocessor.h"
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/*! \brief Sets the MCU in the specified sleep mode.
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*
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* \param mode Sleep mode:
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* \arg \c AVR32_PM_SMODE_IDLE: Idle;
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* \arg \c AVR32_PM_SMODE_FROZEN: Frozen;
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* \arg \c AVR32_PM_SMODE_STANDBY: Standby;
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* \arg \c AVR32_PM_SMODE_STOP: Stop;
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* \arg \c AVR32_PM_SMODE_DEEP_STOP: DeepStop;
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* \arg \c AVR32_PM_SMODE_STATIC: Static.
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*/
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#define SLEEP(mode) {__asm__ __volatile__ ("sleep "STRINGZ(mode));}
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//! Input and output parameters when initializing PM clocks using pm_configure_clocks().
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typedef struct
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{
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//! CPU frequency (input/output argument).
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unsigned long cpu_f;
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//! PBA frequency (input/output argument).
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unsigned long pba_f;
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//! Oscillator 0's external crystal(or external clock) frequency (board dependant) (input argument).
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unsigned long osc0_f;
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//! Oscillator 0's external crystal(or external clock) startup time: AVR32_PM_OSCCTRL0_STARTUP_x_RCOSC (input argument).
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unsigned long osc0_startup;
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} pm_freq_param_t;
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#define PM_FREQ_STATUS_FAIL (-1)
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#define PM_FREQ_STATUS_OK (0)
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/*! \brief Gets the MCU reset cause.
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*
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* \param pm Base address of the Power Manager instance (i.e. &AVR32_PM).
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*
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* \return The MCU reset cause which can be masked with the
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* \c AVR32_PM_RCAUSE_x_MASK bit-masks to isolate specific causes.
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*/
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#if (defined __GNUC__)
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__attribute__((__always_inline__))
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#endif
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extern __inline__ unsigned int pm_get_reset_cause(volatile avr32_pm_t *pm)
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{
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return pm->rcause;
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}
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/*!
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* \brief This function will enable the external clock mode of the oscillator 0.
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* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
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*/
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extern void pm_enable_osc0_ext_clock(volatile avr32_pm_t *pm);
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/*!
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* \brief This function will enable the crystal mode of the oscillator 0.
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* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
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* \param fosc0 Oscillator 0 crystal frequency (Hz)
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*/
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extern void pm_enable_osc0_crystal(volatile avr32_pm_t *pm, unsigned int fosc0);
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/*!
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* \brief This function will enable the oscillator 0 to be used with a startup time.
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* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
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* \param startup Clock 0 startup time. AVR32_PM_OSCCTRL0_STARTUP_x_RCOSC.
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*/
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extern void pm_enable_clk0(volatile avr32_pm_t *pm, unsigned int startup);
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/*!
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* \brief This function will disable the oscillator 0.
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* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
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*/
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extern void pm_disable_clk0(volatile avr32_pm_t *pm);
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/*!
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* \brief This function will enable the oscillator 0 to be used with no startup time.
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* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
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* \param startup Clock 0 startup time, for which the function does not wait. AVR32_PM_OSCCTRL0_STARTUP_x_RCOSC.
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*/
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extern void pm_enable_clk0_no_wait(volatile avr32_pm_t *pm, unsigned int startup);
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/*!
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* \brief This function will wait until the Osc0 clock is ready.
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* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
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*/
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extern void pm_wait_for_clk0_ready(volatile avr32_pm_t *pm);
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/*!
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* \brief This function will enable the external clock mode of the oscillator 1.
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* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
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*/
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extern void pm_enable_osc1_ext_clock(volatile avr32_pm_t *pm);
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/*!
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* \brief This function will enable the crystal mode of the oscillator 1.
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* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
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* \param fosc1 Oscillator 1 crystal frequency (Hz)
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*/
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extern void pm_enable_osc1_crystal(volatile avr32_pm_t *pm, unsigned int fosc1);
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/*!
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* \brief This function will enable the oscillator 1 to be used with a startup time.
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* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
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* \param startup Clock 1 startup time. AVR32_PM_OSCCTRL1_STARTUP_x_RCOSC.
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*/
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extern void pm_enable_clk1(volatile avr32_pm_t *pm, unsigned int startup);
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/*!
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* \brief This function will disable the oscillator 1.
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* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
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*/
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extern void pm_disable_clk1(volatile avr32_pm_t *pm);
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/*!
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* \brief This function will enable the oscillator 1 to be used with no startup time.
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* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
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* \param startup Clock 1 startup time, for which the function does not wait. AVR32_PM_OSCCTRL1_STARTUP_x_RCOSC.
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*/
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extern void pm_enable_clk1_no_wait(volatile avr32_pm_t *pm, unsigned int startup);
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/*!
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* \brief This function will wait until the Osc1 clock is ready.
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* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
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*/
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extern void pm_wait_for_clk1_ready(volatile avr32_pm_t *pm);
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/*!
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* \brief This function will enable the external clock mode of the 32-kHz oscillator.
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* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
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*/
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extern void pm_enable_osc32_ext_clock(volatile avr32_pm_t *pm);
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/*!
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* \brief This function will enable the crystal mode of the 32-kHz oscillator.
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* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
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*/
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extern void pm_enable_osc32_crystal(volatile avr32_pm_t *pm);
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/*!
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* \brief This function will enable the oscillator 32 to be used with a startup time.
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* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
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* \param startup Clock 32 kHz startup time. AVR32_PM_OSCCTRL32_STARTUP_x_RCOSC.
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*/
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extern void pm_enable_clk32(volatile avr32_pm_t *pm, unsigned int startup);
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/*!
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* \brief This function will disable the oscillator 32.
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* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
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*/
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extern void pm_disable_clk32(volatile avr32_pm_t *pm);
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/*!
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* \brief This function will enable the oscillator 32 to be used with no startup time.
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* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
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* \param startup Clock 32 kHz startup time, for which the function does not wait. AVR32_PM_OSCCTRL32_STARTUP_x_RCOSC.
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*/
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extern void pm_enable_clk32_no_wait(volatile avr32_pm_t *pm, unsigned int startup);
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/*!
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* \brief This function will wait until the osc32 clock is ready.
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* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
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*/
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extern void pm_wait_for_clk32_ready(volatile avr32_pm_t *pm);
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/*!
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* \brief This function will select all the power manager clocks.
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* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
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* \param pbadiv Peripheral Bus A clock divisor enable
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* \param pbasel Peripheral Bus A select
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* \param pbbdiv Peripheral Bus B clock divisor enable
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* \param pbbsel Peripheral Bus B select
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* \param hsbdiv High Speed Bus clock divisor enable (CPU clock = HSB clock)
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* \param hsbsel High Speed Bus select (CPU clock = HSB clock )
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*/
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extern void pm_cksel(volatile avr32_pm_t *pm, unsigned int pbadiv, unsigned int pbasel, unsigned int pbbdiv, unsigned int pbbsel, unsigned int hsbdiv, unsigned int hsbsel);
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/*!
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* \brief This function will setup a generic clock.
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* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
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* \param gc generic clock number (0 for gc0...)
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* \param osc_or_pll Use OSC (=0) or PLL (=1)
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* \param pll_osc Select Osc0/PLL0 or Osc1/PLL1
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* \param diven Generic clock divisor enable
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* \param div Generic clock divisor
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*/
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extern void pm_gc_setup(volatile avr32_pm_t *pm, unsigned int gc, unsigned int osc_or_pll, unsigned int pll_osc, unsigned int diven, unsigned int div);
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/*!
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* \brief This function will enable a generic clock.
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* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
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* \param gc generic clock number (0 for gc0...)
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*/
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extern void pm_gc_enable(volatile avr32_pm_t *pm, unsigned int gc);
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/*!
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* \brief This function will disable a generic clock.
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* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
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* \param gc generic clock number (0 for gc0...)
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*/
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extern void pm_gc_disable(volatile avr32_pm_t *pm, unsigned int gc);
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/*!
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* \brief This function will setup a PLL.
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* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
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* \param pll PLL number(0 for PLL0, 1 for PLL1)
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* \param mul PLL MUL in the PLL formula
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* \param div PLL DIV in the PLL formula
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* \param osc OSC number (0 for osc0, 1 for osc1)
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* \param lockcount PLL lockount
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*/
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extern void pm_pll_setup(volatile avr32_pm_t *pm, unsigned int pll, unsigned int mul, unsigned int div, unsigned int osc, unsigned int lockcount);
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/*!
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* \brief This function will set a PLL option.
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* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
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* \param pll PLL number(0 for PLL0, 1 for PLL1)
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* \param pll_freq Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz.
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* \param pll_div2 Divide the PLL output frequency by 2 (this settings does not change the FVCO value)
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* \param pll_wbwdisable 1 Disable the Wide-Bandith Mode (Wide-Bandwith mode allow a faster startup time and out-of-lock time). 0 to enable the Wide-Bandith Mode.
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*/
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extern void pm_pll_set_option(volatile avr32_pm_t *pm, unsigned int pll, unsigned int pll_freq, unsigned int pll_div2, unsigned int pll_wbwdisable);
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/*!
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* \brief This function will get a PLL option.
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* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
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* \param pll PLL number(0 for PLL0, 1 for PLL1)
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* \return Option
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*/
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extern unsigned int pm_pll_get_option(volatile avr32_pm_t *pm, unsigned int pll);
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/*!
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* \brief This function will enable a PLL.
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* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
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* \param pll PLL number(0 for PLL0, 1 for PLL1)
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*/
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extern void pm_pll_enable(volatile avr32_pm_t *pm, unsigned int pll);
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/*!
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* \brief This function will disable a PLL.
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* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
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* \param pll PLL number(0 for PLL0, 1 for PLL1)
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*/
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extern void pm_pll_disable(volatile avr32_pm_t *pm, unsigned int pll);
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/*!
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* \brief This function will wait for PLL0 locked
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* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
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*/
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extern void pm_wait_for_pll0_locked(volatile avr32_pm_t *pm);
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/*!
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* \brief This function will wait for PLL1 locked
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* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
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*/
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extern void pm_wait_for_pll1_locked(volatile avr32_pm_t *pm);
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/*!
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* \brief This function will switch the power manager main clock.
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* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
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* \param clock Clock to be switched on. AVR32_PM_MCSEL_SLOW for RCOsc, AVR32_PM_MCSEL_OSC0 for Osc0, AVR32_PM_MCSEL_PLL0 for PLL0.
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*/
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extern void pm_switch_to_clock(volatile avr32_pm_t *pm, unsigned long clock);
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/*!
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* \brief Switch main clock to clock Osc0 (crystal mode)
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* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
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* \param fosc0 Oscillator 0 crystal frequency (Hz)
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* \param startup Crystal 0 startup time. AVR32_PM_OSCCTRL0_STARTUP_x_RCOSC.
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*/
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extern void pm_switch_to_osc0(volatile avr32_pm_t *pm, unsigned int fosc0, unsigned int startup);
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/*! \brief Enables the Brown-Out Detector interrupt.
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*
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* \param pm Base address of the Power Manager (i.e. &AVR32_PM).
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*/
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extern void pm_bod_enable_irq(volatile avr32_pm_t *pm);
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/*! \brief Disables the Brown-Out Detector interrupt.
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*
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* \param pm Base address of the Power Manager (i.e. &AVR32_PM).
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*/
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extern void pm_bod_disable_irq(volatile avr32_pm_t *pm);
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/*! \brief Clears the Brown-Out Detector interrupt flag.
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*
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* \param pm Base address of the Power Manager (i.e. &AVR32_PM).
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*/
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extern void pm_bod_clear_irq(volatile avr32_pm_t *pm);
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/*! \brief Gets the Brown-Out Detector interrupt flag.
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*
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* \param pm Base address of the Power Manager (i.e. &AVR32_PM).
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*
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* \retval 0 No BOD interrupt.
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* \retval 1 BOD interrupt pending.
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*/
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extern unsigned long pm_bod_get_irq_status(volatile avr32_pm_t *pm);
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/*! \brief Gets the Brown-Out Detector interrupt enable status.
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*
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* \param pm Base address of the Power Manager (i.e. &AVR32_PM).
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*
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* \retval 0 BOD interrupt disabled.
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* \retval 1 BOD interrupt enabled.
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*/
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extern unsigned long pm_bod_get_irq_enable_bit(volatile avr32_pm_t *pm);
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/*! \brief Gets the triggering threshold of the Brown-Out Detector.
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*
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* \param pm Base address of the Power Manager (i.e. &AVR32_PM).
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*
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* \return Triggering threshold of the BOD. See the electrical characteristics
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* in the part datasheet for actual voltage levels.
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*/
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extern unsigned long pm_bod_get_level(volatile avr32_pm_t *pm);
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/*!
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* \brief Read the content of the PM GPLP registers
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* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
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* \param gplp GPLP register index (0,1,... depending on the number of GPLP registers for a given part)
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*
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* \return The content of the chosen GPLP register.
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*/
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extern unsigned long pm_read_gplp(volatile avr32_pm_t *pm, unsigned long gplp);
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/*!
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* \brief Write into the PM GPLP registers
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* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
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* \param gplp GPLP register index (0,1,... depending on the number of GPLP registers for a given part)
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* \param value Value to write
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*/
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extern void pm_write_gplp(volatile avr32_pm_t *pm, unsigned long gplp, unsigned long value);
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/*! \brief Enable the clock of a module.
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*
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* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
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* \param module The module to clock (use one of the defines in the part-specific
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* header file under "toolchain folder"/avr32/inc(lude)/avr32/; depending on the
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* clock domain, look for the sections "CPU clocks", "HSB clocks", "PBx clocks")
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*
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* \return Status.
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* \retval 0 Success.
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* \retval <0 An error occured.
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*/
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extern long pm_enable_module(volatile avr32_pm_t *pm, unsigned long module);
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/*! \brief Disable the clock of a module.
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*
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* \param pm Base address of the Power Manager (i.e. &AVR32_PM)
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* \param module The module to shut down (use one of the defines in the part-specific
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* header file under "toolchain folder"/avr32/inc(lude)/avr32/; depending on the
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* clock domain, look for the sections "CPU clocks", "HSB clocks", "PBx clocks")
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*
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* \return Status.
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* \retval 0 Success.
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* \retval <0 An error occured.
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*/
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extern long pm_disable_module(volatile avr32_pm_t *pm, unsigned long module);
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/*! \brief Automatically configure the CPU, PBA, PBB, and HSB clocks
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* according to the user wishes.
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*
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* This function needs some parameters stored in a pm_freq_param_t structure:
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* - cpu_f and pba_f are the wanted frequencies,
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* - osc0_f is the oscillator 0 on-board frequency (e.g. FOSC0),
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* - osc0_startup is the oscillator 0 startup time (e.g. OSC0_STARTUP).
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*
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* The function will then configure the clocks using the following rules:
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* - It first try to find a valid PLL frequency (the highest possible value to avoid jitter) in order
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* to satisfy the CPU frequency,
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* - It optimizes the configuration depending the various divide stages,
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* - Then, the PBA frequency is configured from the CPU freq.
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* - Note that HSB and PBB are configured with the same frequency as CPU.
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* - Note also that the number of wait states of the flash read accesses is automatically set-up depending
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* the CPU frequency. As a consequence, the application needs the FLASHC driver to compile.
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*
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* The CPU, HSB and PBA frequencies programmed after configuration are stored back into cpu_f and pba_f.
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*
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* \param param pointer on the configuration structure.
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*
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* \retval PM_FREQ_STATUS_OK Mode successfully initialized.
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* \retval PM_FREQ_STATUS_FAIL The configuration can not be done.
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*/
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extern int pm_configure_clocks(pm_freq_param_t *param);
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/*! \brief Automatically configure the USB clock.
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*
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* USB clock is configured to 48MHz, using the PLL1 from the Oscillator0, assuming
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* a 12 MHz crystal is connected to it.
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*/
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extern void pm_configure_usb_clock(void);
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#endif // _PM_H_
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