209 lines
10 KiB
C
209 lines
10 KiB
C
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//###########################################################################
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//
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// FILE: hw_uart.h
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//
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// TITLE: Definitions for the C28x SCI registers.
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//
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//###########################################################################
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// $TI Release: F2837xD Support Library v3.05.00.00 $
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// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $
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// $Copyright:
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// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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#ifndef __HW_UART_H__
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#define __HW_UART_H__
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//*****************************************************************************
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//
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// The following are defines for the SCI register offsets
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//
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//*****************************************************************************
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#define UART_O_CCR 0x0 // Communications control register
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#define UART_O_CTL1 0x1 // Control register 1
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#define UART_O_HBAUD 0x2 // Baud rate (high) register
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#define UART_O_LBAUD 0x3 // Baud rate (low) register
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#define UART_O_CTL2 0x4 // Control register 2
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#define UART_O_RXST 0x5 // Receive status register
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#define UART_O_RXEMU 0x6 // Receive emulation buffer
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// register
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#define UART_O_RXBUF 0x7 // Receive data buffer
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#define UART_O_TXBUF 0x9 // Transmit data buffer
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#define UART_O_FFTX 0xA // FIFO transmit register
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#define UART_O_FFRX 0xB // FIFO receive register
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#define UART_O_FFCT 0xC // FIFO control register
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#define UART_O_PRI 0xF // FIFO Priority control
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SCICCR register
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//
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//*****************************************************************************
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#define UART_CCR_SCICHAR_S 0
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#define UART_CCR_SCICHAR_M 0x7 // Character length control
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#define UART_CCR_ADDRIDLE_MODE 0x8 // ADDR/IDLE Mode control
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#define UART_CCR_LOOPBKENA 0x10 // Loop Back enable
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#define UART_CCR_PARITYENA 0x20 // Parity enable
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#define UART_CCR_PARITY 0x40 // Even or Odd Parity
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#define UART_CCR_STOPBITS 0x80 // Number of Stop Bits
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SCICTL1 register
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//
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//*****************************************************************************
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#define UART_CTL1_RXENA 0x1 // SCI receiver enable
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#define UART_CTL1_TXENA 0x2 // SCI transmitter enable
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#define UART_CTL1_SLEEP 0x4 // SCI sleep
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#define UART_CTL1_TXWAKE 0x8 // Transmitter wakeup method
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#define UART_CTL1_SWRESET 0x20 // Software reset
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#define UART_CTL1_RXERRINTENA 0x40 // Receive __interrupt enable
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SCIHBAUD register
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//
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//*****************************************************************************
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#define UART_HBAUD_BAUD_S 0
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#define UART_HBAUD_BAUD_M 0xFFFF // SCI 16-bit baud selection
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// Registers SCIHBAUD
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SCILBAUD register
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//
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//*****************************************************************************
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#define UART_LBAUD_BAUD_S 0
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#define UART_LBAUD_BAUD_M 0xFFFF // SCI 16-bit baud selection
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// Registers SCILBAUD
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SCICTL2 register
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//
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//*****************************************************************************
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#define UART_CTL2_TXINTENA 0x1 // Transmit __interrupt enable
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#define UART_CTL2_RXBKINTENA 0x2 // Receiver-buffer break enable
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#define UART_CTL2_TXEMPTY 0x40 // Transmitter empty flag
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#define UART_CTL2_TXRDY 0x80 // Transmitter ready flag
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SCIRXST register
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//
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//*****************************************************************************
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#define UART_RXST_RXWAKE 0x2 // Receiver wakeup detect flag
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#define UART_RXST_PE 0x4 // Parity error flag
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#define UART_RXST_OE 0x8 // Overrun error flag
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#define UART_RXST_FE 0x10 // Framing error flag
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#define UART_RXST_BRKDT 0x20 // Break-detect flag
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#define UART_RXST_RXRDY 0x40 // Receiver ready flag
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#define UART_RXST_RXERROR 0x80 // Receiver error flag
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SCIRXEMU register
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//
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//*****************************************************************************
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#define UART_RXEMU_ERXDT_S 0
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#define UART_RXEMU_ERXDT_M 0xFF // Receive emulation buffer data
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SCIRXBUF register
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//
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//*****************************************************************************
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#define UART_RXBUF_SAR_S 0
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#define UART_RXBUF_SAR_M 0xFF // Receive Character bits
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#define UART_RXBUF_SCIFFPE 0x4000 // Receiver error flag
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#define UART_RXBUF_SCIFFFE 0x8000 // Receiver error flag
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SCITXBUF register
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//
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//*****************************************************************************
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#define UART_TXBUF_TXDT_S 0
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#define UART_TXBUF_TXDT_M 0xFF // Transmit data buffer
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SCIFFTX register
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//
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//*****************************************************************************
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#define UART_FFTX_TXFFIL_S 0
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#define UART_FFTX_TXFFIL_M 0x1F // Interrupt level
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#define UART_FFTX_TXFFIENA 0x20 // Interrupt enable
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#define UART_FFTX_TXFFINTCLR 0x40 // Clear INT flag
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#define UART_FFTX_TXFFINT 0x80 // INT flag
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#define UART_FFTX_TXFFST_S 8
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#define UART_FFTX_TXFFST_M 0x1F00 // FIFO status
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#define UART_FFTX_TXFIFORESET 0x2000 // FIFO reset
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#define UART_FFTX_SCIFFENA 0x4000 // Enhancement enable
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#define UART_FFTX_SCIRST 0x8000 // SCI reset rx/tx channels
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SCIFFRX register
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//
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//*****************************************************************************
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#define UART_FFRX_RXFFIL_S 0
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#define UART_FFRX_RXFFIL_M 0x1F // Interrupt level
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#define UART_FFRX_RXFFIENA 0x20 // Interrupt enable
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#define UART_FFRX_RXFFINTCLR 0x40 // Clear INT flag
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#define UART_FFRX_RXFFINT 0x80 // INT flag
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#define UART_FFRX_RXFFST_S 8
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#define UART_FFRX_RXFFST_M 0x1F00 // FIFO status
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#define UART_FFRX_RXFIFORESET 0x2000 // FIFO reset
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#define UART_FFRX_RXFFOVRCLR 0x4000 // Clear overflow
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#define UART_FFRX_RXFFOVF 0x8000 // FIFO overflow
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SCIFFCT register
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//
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//*****************************************************************************
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#define UART_FFCT_FFTXDLY_S 0
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#define UART_FFCT_FFTXDLY_M 0xFF // FIFO transmit delay
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#define UART_FFCT_CDC 0x2000 // Auto baud mode enable
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#define UART_FFCT_ABDCLR 0x4000 // Auto baud clear
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#define UART_FFCT_ABD 0x8000 // Auto baud detect
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the SCIPRI register
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//
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//*****************************************************************************
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#define UART_PRI_FREESOFT_S 3
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#define UART_PRI_FREESOFT_M 0x18 // Emulation modes
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#endif
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