371 lines
12 KiB
C
371 lines
12 KiB
C
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/*
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* Copyright (c) 2015, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "fsl_adc16.h"
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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/*!
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* @brief Get instance number for ADC16 module.
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*
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* @param base ADC16 peripheral base address
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*/
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static uint32_t ADC16_GetInstance(ADC_Type *base);
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/*! @brief Pointers to ADC16 bases for each instance. */
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static ADC_Type *const s_adc16Bases[] = ADC_BASE_PTRS;
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/*! @brief Pointers to ADC16 clocks for each instance. */
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static const clock_ip_name_t s_adc16Clocks[] = ADC16_CLOCKS;
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/*******************************************************************************
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* Code
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******************************************************************************/
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static uint32_t ADC16_GetInstance(ADC_Type *base)
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{
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uint32_t instance;
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/* Find the instance index from base address mappings. */
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for (instance = 0; instance < ARRAY_SIZE(s_adc16Bases); instance++)
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{
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if (s_adc16Bases[instance] == base)
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{
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break;
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}
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}
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assert(instance < ARRAY_SIZE(s_adc16Bases));
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return instance;
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}
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void ADC16_Init(ADC_Type *base, const adc16_config_t *config)
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{
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assert(NULL != config);
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uint32_t tmp32;
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Enable the clock. */
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CLOCK_EnableClock(s_adc16Clocks[ADC16_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/* ADCx_CFG1. */
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tmp32 = ADC_CFG1_ADICLK(config->clockSource) | ADC_CFG1_MODE(config->resolution);
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if (kADC16_LongSampleDisabled != config->longSampleMode)
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{
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tmp32 |= ADC_CFG1_ADLSMP_MASK;
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}
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tmp32 |= ADC_CFG1_ADIV(config->clockDivider);
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if (config->enableLowPower)
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{
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tmp32 |= ADC_CFG1_ADLPC_MASK;
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}
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base->CFG1 = tmp32;
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/* ADCx_CFG2. */
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tmp32 = base->CFG2 & ~(ADC_CFG2_ADACKEN_MASK | ADC_CFG2_ADHSC_MASK | ADC_CFG2_ADLSTS_MASK);
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if (kADC16_LongSampleDisabled != config->longSampleMode)
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{
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tmp32 |= ADC_CFG2_ADLSTS(config->longSampleMode);
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}
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if (config->enableHighSpeed)
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{
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tmp32 |= ADC_CFG2_ADHSC_MASK;
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}
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if (config->enableAsynchronousClock)
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{
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tmp32 |= ADC_CFG2_ADACKEN_MASK;
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}
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base->CFG2 = tmp32;
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/* ADCx_SC2. */
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tmp32 = base->SC2 & ~(ADC_SC2_REFSEL_MASK);
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tmp32 |= ADC_SC2_REFSEL(config->referenceVoltageSource);
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base->SC2 = tmp32;
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/* ADCx_SC3. */
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if (config->enableContinuousConversion)
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{
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base->SC3 |= ADC_SC3_ADCO_MASK;
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}
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else
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{
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base->SC3 &= ~ADC_SC3_ADCO_MASK;
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}
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}
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void ADC16_Deinit(ADC_Type *base)
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{
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Disable the clock. */
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CLOCK_DisableClock(s_adc16Clocks[ADC16_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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}
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void ADC16_GetDefaultConfig(adc16_config_t *config)
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{
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assert(NULL != config);
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config->referenceVoltageSource = kADC16_ReferenceVoltageSourceVref;
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config->clockSource = kADC16_ClockSourceAsynchronousClock;
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config->enableAsynchronousClock = true;
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config->clockDivider = kADC16_ClockDivider8;
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config->resolution = kADC16_ResolutionSE12Bit;
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config->longSampleMode = kADC16_LongSampleDisabled;
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config->enableHighSpeed = false;
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config->enableLowPower = false;
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config->enableContinuousConversion = false;
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}
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#if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION
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status_t ADC16_DoAutoCalibration(ADC_Type *base)
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{
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bool bHWTrigger = false;
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volatile uint32_t tmp32; /* 'volatile' here is for the dummy read of ADCx_R[0] register. */
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status_t status = kStatus_Success;
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/* The calibration would be failed when in hardwar mode.
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* Remember the hardware trigger state here and restore it later if the hardware trigger is enabled.*/
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if (0U != (ADC_SC2_ADTRG_MASK & base->SC2))
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{
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bHWTrigger = true;
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base->SC2 &= ~ADC_SC2_ADTRG_MASK;
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}
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/* Clear the CALF and launch the calibration. */
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base->SC3 |= ADC_SC3_CAL_MASK | ADC_SC3_CALF_MASK;
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while (0U == (kADC16_ChannelConversionDoneFlag & ADC16_GetChannelStatusFlags(base, 0U)))
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{
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/* Check the CALF when the calibration is active. */
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if (0U != (kADC16_CalibrationFailedFlag & ADC16_GetStatusFlags(base)))
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{
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status = kStatus_Fail;
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break;
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}
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}
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tmp32 = base->R[0]; /* Dummy read to clear COCO caused by calibration. */
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/* Restore the hardware trigger setting if it was enabled before. */
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if (bHWTrigger)
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{
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base->SC2 |= ADC_SC2_ADTRG_MASK;
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}
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/* Check the CALF at the end of calibration. */
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if (0U != (kADC16_CalibrationFailedFlag & ADC16_GetStatusFlags(base)))
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{
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status = kStatus_Fail;
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}
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if (kStatus_Success != status) /* Check if the calibration process is succeed. */
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{
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return status;
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}
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/* Calculate the calibration values. */
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tmp32 = base->CLP0 + base->CLP1 + base->CLP2 + base->CLP3 + base->CLP4 + base->CLPS;
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tmp32 = 0x8000U | (tmp32 >> 1U);
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base->PG = tmp32;
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#if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE
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tmp32 = base->CLM0 + base->CLM1 + base->CLM2 + base->CLM3 + base->CLM4 + base->CLMS;
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tmp32 = 0x8000U | (tmp32 >> 1U);
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base->MG = tmp32;
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#endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */
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return kStatus_Success;
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}
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#endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */
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#if defined(FSL_FEATURE_ADC16_HAS_MUX_SELECT) && FSL_FEATURE_ADC16_HAS_MUX_SELECT
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void ADC16_SetChannelMuxMode(ADC_Type *base, adc16_channel_mux_mode_t mode)
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{
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if (kADC16_ChannelMuxA == mode)
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{
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base->CFG2 &= ~ADC_CFG2_MUXSEL_MASK;
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}
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else /* kADC16_ChannelMuxB. */
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{
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base->CFG2 |= ADC_CFG2_MUXSEL_MASK;
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}
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}
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#endif /* FSL_FEATURE_ADC16_HAS_MUX_SELECT */
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void ADC16_SetHardwareCompareConfig(ADC_Type *base, const adc16_hardware_compare_config_t *config)
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{
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uint32_t tmp32 = base->SC2 & ~(ADC_SC2_ACFE_MASK | ADC_SC2_ACFGT_MASK | ADC_SC2_ACREN_MASK);
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if (!config) /* Pass "NULL" to disable the feature. */
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{
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base->SC2 = tmp32;
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return;
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}
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/* Enable the feature. */
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tmp32 |= ADC_SC2_ACFE_MASK;
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/* Select the hardware compare working mode. */
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switch (config->hardwareCompareMode)
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{
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case kADC16_HardwareCompareMode0:
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break;
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case kADC16_HardwareCompareMode1:
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tmp32 |= ADC_SC2_ACFGT_MASK;
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break;
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case kADC16_HardwareCompareMode2:
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tmp32 |= ADC_SC2_ACREN_MASK;
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break;
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case kADC16_HardwareCompareMode3:
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tmp32 |= ADC_SC2_ACFGT_MASK | ADC_SC2_ACREN_MASK;
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break;
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default:
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break;
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}
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base->SC2 = tmp32;
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/* Load the compare values. */
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base->CV1 = ADC_CV1_CV(config->value1);
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base->CV2 = ADC_CV2_CV(config->value2);
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}
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#if defined(FSL_FEATURE_ADC16_HAS_HW_AVERAGE) && FSL_FEATURE_ADC16_HAS_HW_AVERAGE
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void ADC16_SetHardwareAverage(ADC_Type *base, adc16_hardware_average_mode_t mode)
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{
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uint32_t tmp32 = base->SC3 & ~(ADC_SC3_AVGE_MASK | ADC_SC3_AVGS_MASK);
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if (kADC16_HardwareAverageDisabled != mode)
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{
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tmp32 |= ADC_SC3_AVGE_MASK | ADC_SC3_AVGS(mode);
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}
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base->SC3 = tmp32;
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}
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#endif /* FSL_FEATURE_ADC16_HAS_HW_AVERAGE */
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#if defined(FSL_FEATURE_ADC16_HAS_PGA) && FSL_FEATURE_ADC16_HAS_PGA
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void ADC16_SetPGAConfig(ADC_Type *base, const adc16_pga_config_t *config)
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{
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uint32_t tmp32;
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if (!config) /* Passing "NULL" is to disable the feature. */
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{
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base->PGA = 0U;
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return;
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}
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/* Enable the PGA and set the gain value. */
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tmp32 = ADC_PGA_PGAEN_MASK | ADC_PGA_PGAG(config->pgaGain);
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/* Configure the misc features for PGA. */
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if (config->enableRunInNormalMode)
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{
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tmp32 |= ADC_PGA_PGALPb_MASK;
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}
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#if defined(FSL_FEATURE_ADC16_HAS_PGA_CHOPPING) && FSL_FEATURE_ADC16_HAS_PGA_CHOPPING
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if (config->disablePgaChopping)
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{
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tmp32 |= ADC_PGA_PGACHPb_MASK;
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}
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#endif /* FSL_FEATURE_ADC16_HAS_PGA_CHOPPING */
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#if defined(FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT) && FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT
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if (config->enableRunInOffsetMeasurement)
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{
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tmp32 |= ADC_PGA_PGAOFSM_MASK;
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}
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#endif /* FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT */
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base->PGA = tmp32;
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}
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#endif /* FSL_FEATURE_ADC16_HAS_PGA */
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uint32_t ADC16_GetStatusFlags(ADC_Type *base)
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{
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uint32_t ret = 0;
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if (0U != (base->SC2 & ADC_SC2_ADACT_MASK))
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{
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ret |= kADC16_ActiveFlag;
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}
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#if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION
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if (0U != (base->SC3 & ADC_SC3_CALF_MASK))
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{
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ret |= kADC16_CalibrationFailedFlag;
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}
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#endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */
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return ret;
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}
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void ADC16_ClearStatusFlags(ADC_Type *base, uint32_t mask)
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{
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#if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION
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if (0U != (mask & kADC16_CalibrationFailedFlag))
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{
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base->SC3 |= ADC_SC3_CALF_MASK;
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}
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#endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */
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}
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void ADC16_SetChannelConfig(ADC_Type *base, uint32_t channelGroup, const adc16_channel_config_t *config)
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{
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assert(channelGroup < ADC_SC1_COUNT);
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assert(NULL != config);
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uint32_t sc1 = ADC_SC1_ADCH(config->channelNumber); /* Set the channel number. */
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#if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE
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/* Enable the differential conversion. */
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if (config->enableDifferentialConversion)
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{
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|
sc1 |= ADC_SC1_DIFF_MASK;
|
||
|
|
}
|
||
|
|
#endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */
|
||
|
|
/* Enable the interrupt when the conversion is done. */
|
||
|
|
if (config->enableInterruptOnConversionCompleted)
|
||
|
|
{
|
||
|
|
sc1 |= ADC_SC1_AIEN_MASK;
|
||
|
|
}
|
||
|
|
base->SC1[channelGroup] = sc1;
|
||
|
|
}
|
||
|
|
|
||
|
|
uint32_t ADC16_GetChannelStatusFlags(ADC_Type *base, uint32_t channelGroup)
|
||
|
|
{
|
||
|
|
assert(channelGroup < ADC_SC1_COUNT);
|
||
|
|
|
||
|
|
uint32_t ret = 0U;
|
||
|
|
|
||
|
|
if (0U != (base->SC1[channelGroup] & ADC_SC1_COCO_MASK))
|
||
|
|
{
|
||
|
|
ret |= kADC16_ChannelConversionDoneFlag;
|
||
|
|
}
|
||
|
|
return ret;
|
||
|
|
}
|