2015-09-04 21:58:08 +08:00
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/*
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2021-04-09 10:52:34 +08:00
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* Copyright (c) 2006-2021, RT-Thread Development Team
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2015-09-04 21:58:08 +08:00
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*
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2021-04-09 10:52:34 +08:00
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* SPDX-License-Identifier: Apache-2.0
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2015-09-04 21:58:08 +08:00
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*
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* Change Logs:
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2021-04-09 10:52:34 +08:00
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* Date Author Notes
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* 2010-11-13 weety first version
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2015-09-04 21:58:08 +08:00
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*/
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2015-09-04 12:30:20 +08:00
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#ifndef __DM36X_H__
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#define __DM36X_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <rtthread.h>
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#include "psc.h"
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#include "irqs.h"
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#include "dm365_timer.h"
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/**
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* @addtogroup DM36X
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*/
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/*@{*/
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/*
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* Base register addresses
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*/
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2021-04-09 10:52:34 +08:00
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#define DAVINCI_DMA_3PCC_BASE (0x01C00000)
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#define DAVINCI_DMA_3PTC0_BASE (0x01C10000)
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#define DAVINCI_DMA_3PTC1_BASE (0x01C10400)
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#define DAVINCI_I2C_BASE (0x01C21000)
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#define DAVINCI_TIMER0_BASE (0x01C21400)
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#define DAVINCI_TIMER1_BASE (0x01C21800)
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#define DAVINCI_WDOG_BASE (0x01C21C00)
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#define DAVINCI_PWM0_BASE (0x01C22000)
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#define DAVINCI_PWM1_BASE (0x01C22400)
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#define DAVINCI_PWM2_BASE (0x01C22800)
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#define DAVINCI_SYSTEM_MODULE_BASE (0x01C40000)
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#define DAVINCI_PLL_CNTRL0_BASE (0x01C40800)
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#define DAVINCI_PLL_CNTRL1_BASE (0x01C40C00)
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#define DAVINCI_PWR_SLEEP_CNTRL_BASE (0x01C41000)
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#define DAVINCI_SYSTEM_DFT_BASE (0x01C42000)
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#define DAVINCI_IEEE1394_BASE (0x01C60000)
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#define DAVINCI_USB_OTG_BASE (0x01C64000)
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#define DAVINCI_CFC_ATA_BASE (0x01C66000)
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#define DAVINCI_SPI_BASE (0x01C66800)
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#define DAVINCI_GPIO_BASE (0x01C67000)
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#define DAVINCI_UHPI_BASE (0x01C67800)
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#define DAVINCI_VPSS_REGS_BASE (0x01C70000)
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#define DAVINCI_EMAC_CNTRL_REGS_BASE (0x01C80000)
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#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE (0x01C81000)
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#define DAVINCI_EMAC_WRAPPER_RAM_BASE (0x01C82000)
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#define DAVINCI_MDIO_CNTRL_REGS_BASE (0x01C84000)
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#define DAVINCI_IMCOP_BASE (0x01CC0000)
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#define DAVINCI_ASYNC_EMIF_CNTRL_BASE (0x01E00000)
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#define DAVINCI_VLYNQ_BASE (0x01E01000)
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#define DAVINCI_MCBSP_BASE (0x01E02000)
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#define DAVINCI_MMC_SD_BASE (0x01E10000)
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#define DAVINCI_MS_BASE (0x01E20000)
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#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE (0x02000000)
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#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE (0x04000000)
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#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE (0x06000000)
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#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x08000000)
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#define DAVINCI_VLYNQ_REMOTE_BASE (0x0C000000)
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2015-09-04 12:30:20 +08:00
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/*
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* We can have multiple VLYNQ IPs in our system.
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* Define 'LOW_VLYNQ_CONTROL_BASE' with the VLYNQ
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* IP having lowest base address.
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* Define 'HIGH_VLYNQ_CONTROL_BASE' with the VLYNQ
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* IP having highest base address.
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* In case of only one VLYNQ IP, define only the
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* 'LOW_VLYNQ_CONTROL_BASE'.
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*/
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2021-04-09 10:52:34 +08:00
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#define LOW_VLYNQ_CONTROL_BASE DAVINCI_VLYNQ_BASE
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2015-09-04 12:30:20 +08:00
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2021-04-09 10:52:34 +08:00
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#define DM365_EMAC_BASE (0x01D07000)
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#define DM365_EMAC_CNTRL_OFFSET (0x0000)
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#define DM365_EMAC_CNTRL_MOD_OFFSET (0x3000)
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#define DM365_EMAC_CNTRL_RAM_OFFSET (0x1000)
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#define DM365_EMAC_MDIO_OFFSET (0x4000)
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#define DM365_EMAC_CNTRL_RAM_SIZE (0x2000)
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2015-09-04 12:30:20 +08:00
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/*
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* Macro to access device power control
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*/
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#define DAVINCI_VDD3P3V_PWDN (DAVINCI_SYSTEM_MODULE_BASE + 0x48)
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#define DAVINCI_VSCLKDIS (DAVINCI_SYSTEM_MODULE_BASE + 0x6c)
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/*
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* System module registers
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*/
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2021-04-09 10:52:34 +08:00
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#define PINMUX0 (DAVINCI_SYSTEM_MODULE_BASE + 0x00)
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#define PINMUX1 (DAVINCI_SYSTEM_MODULE_BASE + 0x04)
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#define PINMUX2 (DAVINCI_SYSTEM_MODULE_BASE + 0x08)
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#define PINMUX3 (DAVINCI_SYSTEM_MODULE_BASE + 0x0c)
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#define PINMUX4 (DAVINCI_SYSTEM_MODULE_BASE + 0x10)
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2015-09-04 12:30:20 +08:00
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2021-04-09 10:52:34 +08:00
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#define DM365_ARM_INTMUX (DAVINCI_SYSTEM_MODULE_BASE + 0x18)
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#define DM365_EDMA_EVTMUX (DAVINCI_SYSTEM_MODULE_BASE + 0x1C)
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#define DAVINCI_PUPDCTL1 (DAVINCI_SYSTEM_MODULE_BASE + 0x7C)
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2015-09-04 12:30:20 +08:00
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2021-04-09 10:52:34 +08:00
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#define ASYNC_EMIF_REVID 0x00
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#define ASYNC_EMIF_AWCCR 0x04
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#define ASYNC_EMIF_A1CR 0x10
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#define ASYNC_EMIF_A2CR 0x14
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#define ASYNC_EMIF_A3CR 0x18
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2015-09-04 12:30:20 +08:00
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/*
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* Base register addresses common across DM355 and DM365
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*/
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2021-04-09 10:52:34 +08:00
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#define DM3XX_TIMER2_BASE (0x01C20800)
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#define DM3XX_REALTIME_BASE (0x01C20C00)
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#define DM3XX_PWM3_BASE (0x01C22C00)
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#define DM3XX_SPI_BASE (0x01C66000)
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#define DM3XX_SPI0_BASE DM3XX_SPI_BASE
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#define DM3XX_SPI1_BASE (0x01C66800)
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#define DM3XX_SPI2_BASE (0x01C67800)
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2015-09-04 12:30:20 +08:00
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/*
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* DM365 base register address
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*/
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2021-04-09 10:52:34 +08:00
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#define DM365_DMA_3PTC2_BASE (0x01C10800)
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#define DM365_DMA_3PTC3_BASE (0x01C10C00)
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#define DM365_TIMER3_BASE (0x01C23800)
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#define DM365_ADCIF_BASE (0x01C23C00)
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#define DM365_SPI3_BASE (0x01C68000)
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#define DM365_SPI4_BASE (0x01C23000)
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#define DM365_RTC_BASE (0x01C69000)
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#define DM365_KEYSCAN_BASE (0x01C69400)
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#define DM365_UHPI_BASE (0x01C69800)
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#define DM365_IMCOP_BASE (0x01CA0000)
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#define DM365_MMC_SD1_BASE (0x01D00000)
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#define DM365_MCBSP_BASE (0x01D02000)
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#define DM365_UART1_BASE (0x01D06000)
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#define DM365_EMAC_CNTRL_BASE (0x01D07000)
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#define DM365_EMAC_WRAP_RAM_BASE (0x01D08000)
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#define DM365_EMAC_WRAP_CNTRL_BASE (0x01D0A000)
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#define DM365_EMAC_MDIO_BASE (0x01D0B000)
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#define DM365_VOICE_CODEC_BASE (0x01D0C000)
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#define DM365_ASYNC_EMIF_CNTRL_BASE (0x01D10000)
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#define DM365_MMC_SD0_BASE (0x01D11000)
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#define DM365_MS_BASE (0x01D20000)
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#define DM365_KALEIDO_BASE (0x01E00000)
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#define DAVINCI_UART0_BASE (0x01C20000)
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#define PSC_MDCTL_BASE (0x01c41a00)
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#define PSC_MDSTAT_BASE (0x01c41800)
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#define PSC_PTCMD (0x01c41120)
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#define PSC_PTSTAT (0x01c41128)
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#define DM365_EINT_ENABLE0 0x01c48018
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#define DM365_EINT_ENABLE1 0x01c4801c
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#define davinci_readb(a) (*(volatile unsigned char *)(a))
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#define davinci_readw(a) (*(volatile unsigned short *)(a))
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#define davinci_readl(a) (*(volatile unsigned int *)(a))
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#define davinci_writeb(v,a) (*(volatile unsigned char *)(a) = (v))
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#define davinci_writew(v,a) (*(volatile unsigned short *)(a) = (v))
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#define davinci_writel(v,a) (*(volatile unsigned int *)(a) = (v))
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#define readb(a) davinci_readb(a)
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#define readw(a) davinci_readw(a)
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#define readl(a) davinci_readl(a)
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#define write(v,a) davinci_writeb(v,a)
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#define writew(v,a) davinci_writew(v,a)
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#define writel(v,a) davinci_writel(v,a)
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2015-09-04 12:30:20 +08:00
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/* define timer register struct*/
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typedef struct timer_regs_s {
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2021-04-09 10:52:34 +08:00
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rt_uint32_t pid12; /* 0x0 */
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rt_uint32_t emumgt_clksped; /* 0x4 */
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rt_uint32_t gpint_en; /* 0x8 */
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rt_uint32_t gpdir_dat; /* 0xC */
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rt_uint32_t tim12; /* 0x10 */
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rt_uint32_t tim34; /* 0x14 */
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rt_uint32_t prd12; /* 0x18 */
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rt_uint32_t prd34; /* 0x1C */
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rt_uint32_t tcr; /* 0x20 */
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rt_uint32_t tgcr; /* 0x24 */
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rt_uint32_t wdtcr; /* 0x28 */
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rt_uint32_t tlgc; /* 0x2C */
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rt_uint32_t tlmr; /* 0x30 */
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2015-09-04 12:30:20 +08:00
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} timer_regs_t;
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/*****************************/
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/* CPU Mode */
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/*****************************/
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2021-04-09 10:52:34 +08:00
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#define USERMODE 0x10
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#define FIQMODE 0x11
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#define IRQMODE 0x12
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#define SVCMODE 0x13
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#define ABORTMODE 0x17
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#define UNDEFMODE 0x1b
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#define MODEMASK 0x1f
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#define NOINT 0xc0
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2015-09-04 12:30:20 +08:00
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struct rt_hw_register
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{
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rt_uint32_t cpsr;
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rt_uint32_t r0;
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rt_uint32_t r1;
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rt_uint32_t r2;
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rt_uint32_t r3;
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rt_uint32_t r4;
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rt_uint32_t r5;
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rt_uint32_t r6;
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rt_uint32_t r7;
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rt_uint32_t r8;
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rt_uint32_t r9;
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rt_uint32_t r10;
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rt_uint32_t fp;
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rt_uint32_t ip;
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rt_uint32_t sp;
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rt_uint32_t lr;
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rt_uint32_t pc;
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};
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/*@}*/
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#ifdef __cplusplus
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}
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#endif
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#endif
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