2013-05-24 10:04:51 +08:00
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/** @file sys_selftest.h
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* @brief System Memory Header File
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2013-05-29 16:42:26 +08:00
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* @date 29.May.2013
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* @version 03.05.02
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2013-05-24 10:04:51 +08:00
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*
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* This file contains:
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* - Efuse Self Test Functions
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* .
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* which are relevant for the System driver.
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*/
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/* (c) Texas Instruments 2009-2013, All rights reserved. */
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#ifndef __sys_selftest_H__
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#define __sys_selftest_H__
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#include "reg_pbist.h"
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#include "reg_stc.h"
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#include "reg_efc.h"
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#include "sys_core.h"
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#include "system.h"
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#include "sys_vim.h"
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#include "adc.h"
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#include "can.h"
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#include "mibspi.h"
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#include "het.h"
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#include "htu.h"
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#include "esm.h"
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/* USER CODE BEGIN (0) */
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/* USER CODE END */
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#define flash1bitError (*(volatile uint32 *)(0xF00803F0U))
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#define flash2bitError (*(volatile uint32 *)(0xF00803F8U))
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#define tcramA1bitError (*(volatile uint32 *)(0x08400000U))
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#define tcramA2bitError (*(volatile uint32 *)(0x08400010U))
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#define tcramB1bitError (*(volatile uint32 *)(0x08400008U))
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#define tcramB2bitError (*(volatile uint32 *)(0x08400018U))
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#define tcramA1bit (*(volatile uint32 *)(0x08000000U))
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#define tcramA2bit (*(volatile uint32 *)(0x08000010U))
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#define tcramB1bit (*(volatile uint32 *)(0x08000008U))
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#define tcramB2bit (*(volatile uint32 *)(0x08000018U))
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#define flashBadECC (*(volatile uint32 *)(0x20040000U))
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#define CCMSR (*(volatile uint32 *)(0xFFFFF600U))
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#define CCMKEYR (*(volatile uint32 *)(0xFFFFF604U))
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#define DMA_PARCR (*(volatile uint32 *)(0xFFFFF1A8U))
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#define DMA_PARADDR (*(volatile uint32 *)(0xFFFFF1ACU))
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#define DMARAMLOC (*(volatile uint32 *)(0xFFF80000U))
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#define DMARAMPARLOC (*(volatile uint32 *)(0xFFF80A00U))
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#ifndef __PBIST_H__
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#define __PBIST_H__
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/** @enum pbistPort
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* @brief Alias names for pbist Port number
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*
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* This enumeration is used to provide alias names for the pbist Port number
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* - PBIST_PORT0
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* - PBIST_PORT1
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*/
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enum pbistPort
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{
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PBIST_PORT0 = 0U, /**< Alias for PBIST Port 0 */
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PBIST_PORT1 = 1U /**< Alias for PBIST Port 1 */
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};
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/** @enum pbistAlgo
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* @brief Alias names for pbist Algorithm
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*
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* This enumeration is used to provide alias names for the pbist Algorithm
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* - PBIST_TripleReadSlow
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* - PBIST_TripleReadFast
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* - PBIST_March13N_DP
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* - PBIST_March13N_SP
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* - PBIST_DOWN1a_DP
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* - PBIST_DOWN1a_SP
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* - PBIST_MapColumn_DP
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* - PBIST_MapColumn_SP
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* - PBIST_Precharge_DP
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* - PBIST_Precharge_SP
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* - PBIST_DTXN2a_DP
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* - PBIST_DTXN2a_SP
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* - PBIST_PMOSOpen_DP
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* - PBIST_PMOSOpen_SP
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* - PBIST_PPMOSOpenSlice1_DP
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* - PBIST_PPMOSOpenSlice1_SP
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* - PBIST_PPMOSOpenSlice2_DP
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* - PBIST_PPMOSOpenSlice2_SP
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*/
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enum pbistAlgo
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{
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PBIST_TripleReadSlow = 0x00000001U,
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PBIST_TripleReadFast = 0x00000002U,
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PBIST_March13N_DP = 0x00000004U,
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PBIST_March13N_SP = 0x00000008U,
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PBIST_DOWN1a_DP = 0x00000010U,
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PBIST_DOWN1a_SP = 0x00000020U,
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PBIST_MapColumn_DP = 0x00000040U,
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PBIST_MapColumn_SP = 0x00000080U,
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PBIST_Precharge_DP = 0x00000100U,
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PBIST_Precharge_SP = 0x00000200U,
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PBIST_DTXN2a_DP = 0x00000400U,
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PBIST_DTXN2a_SP = 0x00000800U,
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PBIST_PMOSOpen_DP = 0x00001000U,
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PBIST_PMOSOpen_SP = 0x00002000U,
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PBIST_PPMOSOpenSlice1_DP = 0x00004000U,
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PBIST_PPMOSOpenSlice1_SP = 0x00008000U,
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PBIST_PPMOSOpenSlice2_DP = 0x00010000U,
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PBIST_PPMOSOpenSlice2_SP = 0x00020000U
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};
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/* PBIST configuration registers */
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typedef struct pbist_config_reg
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{
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uint32 CONFIG_RAMT;
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uint32 CONFIG_DLR;
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uint32 CONFIG_PACT;
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uint32 CONFIG_PBISTID;
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uint32 CONFIG_OVER;
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uint32 CONFIG_FSRDL1;
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uint32 CONFIG_ROM;
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uint32 CONFIG_ALGO;
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uint32 CONFIG_RINFOL;
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uint32 CONFIG_RINFOU;
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} pbist_config_reg_t;
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/* PBIST congiruration registers initial value */
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#define PBIST_RAMT_CONFIGVALUE 0U
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#define PBIST_DLR_CONFIGVALUE 0U
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#define PBIST_PACT_CONFIGVALUE 0U
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#define PBIST_PBISTID_CONFIGVALUE 0U
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#define PBIST_OVER_CONFIGVALUE 0U
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#define PBIST_FSRDL1_CONFIGVALUE 0U
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#define PBIST_ROM_CONFIGVALUE 0U
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#define PBIST_ALGO_CONFIGVALUE 0U
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#define PBIST_RINFOL_CONFIGVALUE 0U
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#define PBIST_RINFOU_CONFIGVALUE 0U
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/* USER CODE BEGIN (1) */
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/* USER CODE END */
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/** @fn void memoryPort0TestFailNotification(uint32 groupSelect, uint32 dataSelect, uint32 address, uint32 data)
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* @brief Memory Port 0 test fail notification
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* @param[in] groupSelect Failing Ram group select:
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* @param[in] dataSelect Failing Ram data select:
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* @param[in] address Failing Ram offset:
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* @param[in] data Failing data at address:
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*
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* @note This function has to be provide by the user.
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*/
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void memoryPort0TestFailNotification(uint32 groupSelect, uint32 dataSelect, uint32 address, uint32 data);
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/** @fn void memoryPort1TestFailNotification(uint32 groupSelect, uint32 dataSelect, uint32 address, uint32 data)
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* @brief Memory Port 1 test fail notification
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* @param[in] groupSelect Failing Ram group select:
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* @param[in] dataSelect Failing Ram data select:
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* @param[in] address Failing Ram offset:
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* @param[in] data Failing data at address:
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*
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* @note This function has to be provide by the user.
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*/
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void memoryPort1TestFailNotification(uint32 groupSelect, uint32 dataSelect, uint32 address, uint32 data);
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void pbistGetConfigValue(pbist_config_reg_t *config_reg, config_value_type_t type);
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#endif
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#ifndef __STC_H__
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#define __STC_H__
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/* STC General Definitions */
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/* STC Test Intervals supported in the Device */
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#define STC_INTERVAL 24U
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#define STC_MAX_TIMEOUT 0xFFFFFFFFU
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/* Configuration registers */
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typedef struct stc_config_reg
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{
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uint32 CONFIG_STCGCR0;
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uint32 CONFIG_STCGCR1;
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uint32 CONFIG_STCTPR;
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uint32 CONFIG_STCSCSCR;
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} stc_config_reg_t;
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/* Configuration registers initial value */
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#define STC_STCGCR0_CONFIGVALUE 0xFFFF0000U
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#define STC_STCGCR1_CONFIGVALUE 0x5U
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#define STC_STCTPR_CONFIGVALUE 0xFFFFFFFFU
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#define STC_STCSCSCR_CONFIGVALUE 0x5U
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void stcGetConfigValue(stc_config_reg_t *config_reg, config_value_type_t type);
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#endif
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#ifndef __EFC_H__
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#define __EFC_H__
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#define INPUT_ENABLE 0x0000000FU
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#define INPUT_DISABLE 0x00000000U
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#define SYS_WS_READ_STATES 0x00000000U
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#define SYS_REPAIR_EN_0 0x00000000U
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#define SYS_REPAIR_EN_3 0x00000100U
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#define SYS_REPAIR_EN_5 0x00000200U
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#define SYS_DEID_AUTOLOAD_EN 0x00000400U
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#define EFC_FDI_EN 0x00000800U
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#define EFC_FDI_DIS 0x00000000U
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#define SYS_ECC_OVERRIDE_EN 0x00001000U
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#define SYS_ECC_OVERRIDE_DIS 0x00000000U
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#define SYS_ECC_SELF_TEST_EN 0x00002000U
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#define SYS_ECC_SELF_TEST_DIS 0x00000000U
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#define OUTPUT_ENABLE 0x0003C000U
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#define OUTPUT_DISABLE 0x00000000U
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/*********** OUTPUT **************/
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#define EFC_AUTOLOAD_ERROR_EN 0x00040000U
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#define EFC_INSTRUCTION_ERROR_EN 0x00080000U
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#define EFC_INSTRUCTION_INFO_EN 0x00100000U
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#define EFC_SELF_TEST_ERROR_EN 0x00200000U
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#define EFC_AUTOLOAD_ERROR_DIS 0x00000000U
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#define EFC_INSTRUCTION_ERROR_DIS 0x00000000U
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#define EFC_INSTRUCTION_INFO_DIS 0x00000000U
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#define EFC_SELF_TEST_ERROR_DIS 0x00000000U
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#define DISABLE_READ_ROW0 0x00800000U
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/********************************************************************/
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#define SYS_REPAIR_0 0x00000010U
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#define SYS_REPAIR_3 0x00000010U
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#define SYS_REPAIR_5 0x00000020U
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#define SYS_DEID_AUTOLOAD 0x00000040U
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#define SYS_FCLRZ 0x00000080U
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#define EFC_READY 0x00000100U
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#define SYS_ECC_OVERRIDE 0x00000200U
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#define EFC_AUTOLOAD_ERROR 0x00000400U
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#define EFC_INSTRUCTION_ERROR 0x00000800U
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#define EFC_INSTRUCTION_INFO 0x00001000U
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#define SYS_ECC_SELF_TEST 0x00002000U
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#define EFC_SELF_TEST_ERROR 0x00004000U
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#define EFC_SELF_TEST_DONE 0x00008000U
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/************** 0x3C error status register ******************************************************/
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#define TIME_OUT 0x01
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#define AUTOLOAD_NO_FUSEROM_DATA 0x02U
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#define AUTOLOAD_SIGN_FAIL 0x03U
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#define AUTOLOAD_PROG_INTERRUPT 0x04U
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#define AUTOLOAD_TWO_BIT_ERR 0x05U
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#define PROGRAME_WR_P_SET 0x06U
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#define PROGRAME_MNY_DATA_ITERTN 0x07U
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#define PROGRAME_MNY_CNTR_ITERTN 0x08U
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#define UN_PROGRAME_BIT_SET 0x09U
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#define REDUNDANT_REPAIR_ROW 0x0AU
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#define PROGRAME_MNY_CRA_ITERTN 0x0BU
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#define PROGRAME_SAME_DATA 0x0CU
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#define PROGRAME_CMP_SKIP 0x0DU
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#define PROGRAME_ABORT 0x0EU
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#define PROGRAME_INCORRECT_KEY 0x0FU
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#define FUSEROM_LASTROW_STUCK 0x10U
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#define AUTOLOAD_SINGLE_BIT_ERR 0x15U
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#define DUMPWORD_TWO_BIT_ERR 0x16U
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#define DUMPWORD_ONE_BIT_ERR 0x17U
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#define SELF_TEST_ERROR 0x18U
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#define INSTRUCTION_DONE 0x20U
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/************** Efuse Instruction set ******************************************************/
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#define TEST_UNPROGRAME_ROM 0x01000000U
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#define PROGRAME_CRA 0x02000000U
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#define DUMP_WORD 0x04000000U
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#define LOAD_FUSE_SCAN_CHAIN 0x05000000U
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#define PROGRAME_DATA 0x07000000U
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#define RUN_AUTOLOAD_8 0x08000000U
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#define RUN_AUTOLOAD_A 0x0A000000U
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/* Configuration registers */
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typedef struct efc_config_reg
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{
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uint32 CONFIG_BOUNDARY;
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uint32 CONFIG_PINS;
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uint32 CONFIG_SELFTESTCYCLES;
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uint32 CONFIG_SELFTESTSIGN;
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}efc_config_reg_t;
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/* Configuration registers initial value */
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#define EFC_BOUNDARY_CONFIGVALUE 0x0000200FU
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#define EFC_PINS_CONFIGVALUE 0x000082E0U
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#define EFC_SELFTESTCYCLES_CONFIGVALUE 0x00000258U
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#define EFC_SELFTESTSIGN_CONFIGVALUE 0x5362F97FU
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void efcGetConfigValue(efc_config_reg_t *config_reg, config_value_type_t type);
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#endif
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/* safety Init Interface Functions */
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void ccmSelfCheck(void);
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void ccmFail(uint32 x);
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void stcSelfCheck(void);
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void stcSelfCheckFail(void);
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void cpuSelfTest(uint32 no_of_intervals, uint32 max_timeout, boolean restart_test);
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void cpuSelfTestFail(void);
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void memoryInit(uint32 ram);
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void pbistSelfCheck(void);
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void pbistRun(uint32 raminfoL, uint32 algomask);
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void pbistStop(void);
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void pbistSelfCheckFail(void);
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boolean pbistIsTestCompleted(void);
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boolean pbistIsTestPassed(void);
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boolean pbistPortTestStatus(uint32 port);
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void efcCheck(void);
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void efcSelfTest(void);
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boolean efcStuckZeroTest(void);
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boolean checkefcSelfTest(void);
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void efcClass1Error(void);
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void efcClass2Error(void);
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void fmcBus2Check(void);
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void fmcECCcheck(void);
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void fmcClass1Error(void);
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void fmcClass2Error(void);
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void checkB0RAMECC(void);
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void checkB1RAMECC(void);
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void tcramClass1Error(void);
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void tcramClass2Error(void);
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void checkFlashECC(void);
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void flashClass1Error(void);
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void flashClass2Error(void);
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void vimParityCheck(void);
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void dmaParityCheck(void);
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void adc1ParityCheck(void);
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void adc2ParityCheck(void);
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void het1ParityCheck(void);
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void htu1ParityCheck(void);
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void het2ParityCheck(void);
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void htu2ParityCheck(void);
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void can1ParityCheck(void);
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void can2ParityCheck(void);
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void can3ParityCheck(void);
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void mibspi1ParityCheck(void);
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void mibspi3ParityCheck(void);
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void mibspi5ParityCheck(void);
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/* USER CODE BEGIN (2) */
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/* USER CODE END */
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/* Configuration registers */
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typedef struct ccmr4_config_reg
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|
{
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uint32 CONFIG_CCMKEYR;
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}ccmr4_config_reg_t;
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/* Configuration registers initial value */
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|
#define CCMR4_CCMKEYR_CONFIGVALUE 0U
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void ccmr4GetConfigValue(ccmr4_config_reg_t *config_reg, config_value_type_t type);
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#endif
|
