2013-09-20 21:20:51 +08:00
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/*
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2022-01-18 13:35:13 +08:00
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* Copyright (c) 2006-2022, RT-Thread Development Team
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2013-09-20 21:20:51 +08:00
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*
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2018-10-15 01:35:07 +08:00
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* SPDX-License-Identifier: Apache-2.0
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2013-09-20 21:20:51 +08:00
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*
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* Change Logs:
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* Date Author Notes
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* 2013-07-05 Bernard the first version
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*/
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.equ Mode_USR, 0x10
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.equ Mode_FIQ, 0x11
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.equ Mode_IRQ, 0x12
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.equ Mode_SVC, 0x13
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.equ Mode_ABT, 0x17
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.equ Mode_UND, 0x1B
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.equ Mode_SYS, 0x1F
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.equ I_Bit, 0x80 @ when I bit is set, IRQ is disabled
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.equ F_Bit, 0x40 @ when F bit is set, FIQ is disabled
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2014-08-12 18:26:22 +08:00
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.equ UND_Stack_Size, 0x00000200
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2013-09-20 21:20:51 +08:00
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.equ SVC_Stack_Size, 0x00000100
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.equ ABT_Stack_Size, 0x00000000
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.equ FIQ_Stack_Size, 0x00000000
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.equ IRQ_Stack_Size, 0x00000100
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.equ USR_Stack_Size, 0x00000100
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#define ISR_Stack_Size (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
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FIQ_Stack_Size + IRQ_Stack_Size)
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/* stack */
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.globl stack_start
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.globl stack_top
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2019-10-22 09:47:41 +08:00
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.align 3
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2013-09-20 21:20:51 +08:00
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stack_start:
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.rept ISR_Stack_Size
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.long 0
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.endr
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stack_top:
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/* reset entry */
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.globl _reset
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_reset:
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/* set the cpu to SVC32 mode and disable interrupt */
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mrs r0, cpsr
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bic r0, r0, #0x1f
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orr r0, r0, #0x13
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msr cpsr_c, r0
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/* setup stack */
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bl stack_setup
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/* clear .bss */
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mov r0,#0 /* get a zero */
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ldr r1,=__bss_start /* bss start */
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ldr r2,=__bss_end /* bss end */
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bss_loop:
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cmp r1,r2 /* check if data to clear */
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strlo r0,[r1],#4 /* clear 4 bytes */
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blo bss_loop /* loop until done */
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/* call C++ constructors of global objects */
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ldr r0, =__ctors_start__
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ldr r1, =__ctors_end__
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2022-01-18 13:35:13 +08:00
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2013-09-20 21:20:51 +08:00
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ctor_loop:
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cmp r0, r1
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beq ctor_end
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ldr r2, [r0], #4
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stmfd sp!, {r0-r1}
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mov lr, pc
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bx r2
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ldmfd sp!, {r0-r1}
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b ctor_loop
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ctor_end:
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/* start RT-Thread Kernel */
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ldr pc, _rtthread_startup
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_rtthread_startup:
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.word rtthread_startup
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stack_setup:
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ldr r0, =stack_top
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@ Enter Undefined Instruction Mode and set its Stack Pointer
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msr cpsr_c, #Mode_UND|I_Bit|F_Bit
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mov sp, r0
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sub r0, r0, #UND_Stack_Size
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@ Enter Abort Mode and set its Stack Pointer
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msr cpsr_c, #Mode_ABT|I_Bit|F_Bit
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mov sp, r0
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sub r0, r0, #ABT_Stack_Size
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@ Enter FIQ Mode and set its Stack Pointer
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msr cpsr_c, #Mode_FIQ|I_Bit|F_Bit
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mov sp, r0
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sub r0, r0, #FIQ_Stack_Size
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@ Enter IRQ Mode and set its Stack Pointer
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msr cpsr_c, #Mode_IRQ|I_Bit|F_Bit
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mov sp, r0
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sub r0, r0, #IRQ_Stack_Size
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@ Enter Supervisor Mode and set its Stack Pointer
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msr cpsr_c, #Mode_SVC|I_Bit|F_Bit
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mov sp, r0
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sub r0, r0, #SVC_Stack_Size
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@ Enter User Mode and set its Stack Pointer
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mov sp, r0
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sub sl, sp, #USR_Stack_Size
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bx lr
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/* exception handlers: undef, swi, padt, dabt, resv, irq, fiq */
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.align 5
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.globl vector_undef
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vector_undef:
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sub sp, sp, #72
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stmia sp, {r0 - r12} @/* Calling r0-r12 */
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add r8, sp, #60
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2014-08-12 18:26:22 +08:00
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mrs r1, cpsr
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mrs r2, spsr
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orr r2,r2, #I_Bit|F_Bit
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msr cpsr_c, r2
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mov r0, r0
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stmdb r8, {sp, lr} @/* Calling SP, LR */
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msr cpsr_c, r1 @/* return to Undefined Instruction mode */
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2013-09-20 21:20:51 +08:00
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str lr, [r8, #0] @/* Save calling PC */
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mrs r6, spsr
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str r6, [r8, #4] @/* Save CPSR */
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str r0, [r8, #8] @/* Save OLD_R0 */
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mov r0, sp
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bl rt_hw_trap_udef
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2014-08-12 18:26:22 +08:00
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ldmia sp, {r0 - r12} @/* Calling r0 - r2 */
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mov r0, r0
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ldr lr, [sp, #60] @/* Get PC */
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add sp, sp, #72
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movs pc, lr @/* return & move spsr_svc into cpsr */
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2013-09-20 21:20:51 +08:00
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.align 5
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.globl vector_swi
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vector_swi:
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bl rt_hw_trap_swi
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2022-01-18 13:35:13 +08:00
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.align 5
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2013-09-20 21:20:51 +08:00
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.globl vector_pabt
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vector_pabt:
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bl rt_hw_trap_pabt
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.align 5
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.globl vector_dabt
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vector_dabt:
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sub sp, sp, #72
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stmia sp, {r0 - r12} @/* Calling r0-r12 */
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add r8, sp, #60
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stmdb r8, {sp, lr} @/* Calling SP, LR */
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str lr, [r8, #0] @/* Save calling PC */
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mrs r6, spsr
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str r6, [r8, #4] @/* Save CPSR */
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str r0, [r8, #8] @/* Save OLD_R0 */
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mov r0, sp
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bl rt_hw_trap_dabt
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2014-08-12 18:26:22 +08:00
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ldmia sp, {r0 - r12} @/* Calling r0 - r2 */
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mov r0, r0
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ldr lr, [sp, #60] @/* Get PC */
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add sp, sp, #72
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movs pc, lr @/* return & move spsr_svc into cpsr */
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2013-09-20 21:20:51 +08:00
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.align 5
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.globl vector_resv
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vector_resv:
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b .
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.align 5
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.globl vector_fiq
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vector_fiq:
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stmfd sp!,{r0-r7,lr}
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bl rt_hw_trap_fiq
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ldmfd sp!,{r0-r7,lr}
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subs pc,lr,#4
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.globl rt_interrupt_enter
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.globl rt_interrupt_leave
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.globl rt_thread_switch_interrupt_flag
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.globl rt_interrupt_from_thread
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.globl rt_interrupt_to_thread
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.globl rt_current_thread
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.globl vmm_thread
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.globl vmm_virq_check
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.globl vector_irq
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vector_irq:
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stmfd sp!, {r0-r12,lr}
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bl rt_interrupt_enter
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bl rt_hw_trap_irq
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bl rt_interrupt_leave
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@ if rt_thread_switch_interrupt_flag set, jump to
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@ rt_hw_context_switch_interrupt_do and don't return
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ldr r0, =rt_thread_switch_interrupt_flag
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ldr r1, [r0]
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cmp r1, #1
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beq rt_hw_context_switch_interrupt_do
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ldmfd sp!, {r0-r12,lr}
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subs pc, lr, #4
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rt_hw_context_switch_interrupt_do:
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mov r1, #0 @ clear flag
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str r1, [r0]
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ldmfd sp!, {r0-r12,lr}@ reload saved registers
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stmfd sp, {r0-r2} @ save r0-r2
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mrs r0, spsr @ get cpsr of interrupt thread
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sub r1, sp, #4*3
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sub r2, lr, #4 @ save old task's pc to r2
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@ switch to SVC mode with no interrupt
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msr cpsr_c, #I_Bit|F_Bit|Mode_SVC
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stmfd sp!, {r2} @ push old task's pc
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stmfd sp!, {r3-r12,lr}@ push old task's lr,r12-r4
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ldmfd r1, {r1-r3} @ restore r0-r2 of the interrupt thread
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stmfd sp!, {r1-r3} @ push old task's r0-r2
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stmfd sp!, {r0} @ push old task's cpsr
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ldr r4, =rt_interrupt_from_thread
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ldr r5, [r4]
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str sp, [r5] @ store sp in preempted tasks's TCB
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ldr r6, =rt_interrupt_to_thread
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ldr r6, [r6]
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ldr sp, [r6] @ get new task's stack pointer
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ldmfd sp!, {r4} @ pop new task's cpsr to spsr
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msr spsr_cxsf, r4
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ldmfd sp!, {r0-r12,lr,pc}^ @ pop new task's r0-r12,lr & pc, copy spsr to cpsr
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