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rt-thread-official/bsp/qemu-virt64-riscv/Kconfig

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add qemu-riscv-virt64 bsp add qemu-riscv-virt64 bsp
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mainmenu "RT-Thread Project Configuration"
bsp中option env语句替换为新语句，并同步更新了source "$xxx"语句
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BSP_DIR := .
add qemu-riscv-virt64 bsp add qemu-riscv-virt64 bsp
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bsp中option env语句替换为新语句，并同步更新了source "$xxx"语句
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RTT_DIR := ../../
add qemu-riscv-virt64 bsp add qemu-riscv-virt64 bsp
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bsp中option env语句替换为新语句，并同步更新了source "$xxx"语句
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PKGS_DIR := packages
add qemu-riscv-virt64 bsp add qemu-riscv-virt64 bsp
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bsp中option env语句替换为新语句，并同步更新了source "$xxx"语句
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source "$(RTT_DIR)/Kconfig"
osource "$PKGS_DIR/Kconfig"
rsource "driver/Kconfig"
add qemu-riscv-virt64 bsp add qemu-riscv-virt64 bsp
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sync branch rt-smart. (#6641) * Synchronize the code of the rt mart branch to the master branch. * TTY device * Add lwP code from rt-smart * Add vnode in DFS, but DFS will be re-write for rt-smart * There are three libcpu for rt-smart: * arm/cortex-a, arm/aarch64 * riscv64 Co-authored-by: Rbb666 <zhangbingru@rt-thread.com> Co-authored-by: zhkag <zhkag@foxmail.com>
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config BOARD_QEMU_VIRT_RV64
add qemu-riscv-virt64 bsp add qemu-riscv-virt64 bsp
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bool
select ARCH_RISCV64
[libcpu/rv64] feat: unify tick.c The changes unify the tick.c implementations for all risc-v64 architectures, leveraging the CPUTIME feature. This refactoring was necessary to streamline the codebase, and ensure consistent timer handling across different platforms. Changes: - Updated `Kconfig` in `bsp/cvitek/cv18xx_risc-v` to fix formatting issues. - Updated .config for BSPs to update `CPUTIME_TIMER_FREQ` - Updated header of for API `riscv_cputime_init` - Initialized riscv timer on `rt_hw_tick_init` - Refactored `tick.c` and `tick.h` in `libcpu/risc-v/t-head/c906` and `libcpu/risc-v/virt64`: - Replaced direct use of `rdtime` with `clock_cpu_gettime`. - Removed redundant timer frequency definitions. - Added static assertions to check the value of `CPUTIME_TIMER_FREQ`. - Initialized `tick_cycles` based on `CPUTIME_TIMER_FREQ`. - Integrated `ktime` support for tick initialization. Signed-off-by: Shell <smokewood@qq.com> Reviewed-on: https://github.com/RT-Thread/rt-thread/pull/9164 Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
2024-07-15 12:06:17 +08:00
select ARCH_USING_RISCV_COMMON64
add qemu-riscv-virt64 bsp add qemu-riscv-virt64 bsp
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select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
sync branch rt-smart. (#6641) * Synchronize the code of the rt mart branch to the master branch. * TTY device * Add lwP code from rt-smart * Add vnode in DFS, but DFS will be re-write for rt-smart * There are three libcpu for rt-smart: * arm/cortex-a, arm/aarch64 * riscv64 Co-authored-by: Rbb666 <zhangbingru@rt-thread.com> Co-authored-by: zhkag <zhkag@foxmail.com>
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select RT_USING_CACHE
select ARCH_MM_MMU
[libcpu] rv64: support for ARCH_REMAP_KERNEL (#9067) * [libcpu] support for ARCH_REMAP_KERNEL These changes introduce support for the ARCH_REMAP_KERNEL configuration, which isolates kernel space in high virtual address regions. This feature is necessary to enhance memory protection and management by segregating user and kernel spaces more effectively. Changes: - Updated conditional macros to check for ARCH_REMAP_KERNEL instead of ARCH_KERNEL_IN_HIGH_VA in board initialization files to reflect the new configuration option. - Modified qemu-virt64-riscv Kconfig and SConstruct files to include and utilize ARCH_REMAP_KERNEL. - Created a new linker script `link_smart.lds` for smart linking in qemu-virt64-riscv. - Updated rtconfig.py to use a more flexible execution path setup. - Enhanced user address space definitions in `lwp_arch.h` to support the new virtual address mappings. - Adjusted kernel memory initialization and mapping logic in `c906/mmu.c` and `virt64/mmu.c` to account for high virtual address regions. - Added Kconfig option to enable ARCH_REMAP_KERNEL for RISCV64 architectures. - Enhanced memory setup functions to support new mapping scheme, including updates to early page table setup and address relocation logic. These modifications ensure that the system can utilize high memory addresses for the kernel, improving memory isolation and system stability. Signed-off-by: Shell <smokewood@qq.com> * fixup: CI run failed * bsp: default config without using smart * fixup: static checks * restore rt_hw_mmu_kernel_map_init for D1 --------- Signed-off-by: Shell <smokewood@qq.com>
2024-06-18 11:15:59 +08:00
select ARCH_REMAP_KERNEL
add qemu-riscv-virt64 bsp add qemu-riscv-virt64 bsp
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default y
sync branch rt-smart. (#6641) * Synchronize the code of the rt mart branch to the master branch. * TTY device * Add lwP code from rt-smart * Add vnode in DFS, but DFS will be re-write for rt-smart * There are three libcpu for rt-smart: * arm/cortex-a, arm/aarch64 * riscv64 Co-authored-by: Rbb666 <zhangbingru@rt-thread.com> Co-authored-by: zhkag <zhkag@foxmail.com>
2022-12-03 12:07:44 +08:00
config ENABLE_FPU
bool "Enable FPU"
feat: bsp: qemu risc-v64: fit into common64
2024-09-02 14:23:10 +08:00
select ARCH_RISCV_FPU
sync branch rt-smart. (#6641) * Synchronize the code of the rt mart branch to the master branch. * TTY device * Add lwP code from rt-smart * Add vnode in DFS, but DFS will be re-write for rt-smart * There are three libcpu for rt-smart: * arm/cortex-a, arm/aarch64 * riscv64 Co-authored-by: Rbb666 <zhangbingru@rt-thread.com> Co-authored-by: zhkag <zhkag@foxmail.com>
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default y
config ENABLE_VECTOR
bool "Using RISC-V Vector Extension"
feat: libcpu/risc-v: unify context on c906, virt64 Changes: - added config for NEW_CTX_SWITCH - used new context on c906 sched switch routine - update _rt_hw_stack_init to fit into NEW_CTX_SWITCH - separated vector ctx from the generic Signed-off-by: Shell <smokewood@qq.com>
2024-09-02 16:38:42 +08:00
select ARCH_RISCV_VECTOR
sync branch rt-smart. (#6641) * Synchronize the code of the rt mart branch to the master branch. * TTY device * Add lwP code from rt-smart * Add vnode in DFS, but DFS will be re-write for rt-smart * There are three libcpu for rt-smart: * arm/cortex-a, arm/aarch64 * riscv64 Co-authored-by: Rbb666 <zhangbingru@rt-thread.com> Co-authored-by: zhkag <zhkag@foxmail.com>
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default n
if ENABLE_VECTOR
choice
prompt "Vector Registers Length in Bits"
default ARCH_VECTOR_VLEN_128
format Kconfig and sconscript
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sync branch rt-smart. (#6641) * Synchronize the code of the rt mart branch to the master branch. * TTY device * Add lwP code from rt-smart * Add vnode in DFS, but DFS will be re-write for rt-smart * There are three libcpu for rt-smart: * arm/cortex-a, arm/aarch64 * riscv64 Co-authored-by: Rbb666 <zhangbingru@rt-thread.com> Co-authored-by: zhkag <zhkag@foxmail.com>
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config ARCH_VECTOR_VLEN_128
bool "128"
config ARCH_VECTOR_VLEN_256
bool "256"
endchoice
endif
config RT_USING_USERSPACE_32BIT_LIMIT
bool "Enable userspace 32bit limit"
default n
config RT_USING_VIRTIO_MMIO_ALIGN
bool "Open packed attribution, this may caused an error on virtio"
default n
add qemu-riscv-virt64 bsp add qemu-riscv-virt64 bsp
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config __STACKSIZE__
int "stack size for interrupt"
default 4096