2022-08-14 10:29:05 +08:00
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/*
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2022-08-17 00:43:24 +08:00
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* Copyright (c) 2006-2022, Synwit Technology Co.,Ltd.
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2022-08-14 10:29:05 +08:00
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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2022-08-17 00:43:24 +08:00
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* 2018-05-31 ZYH first version
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* 2018-12-10 Zohar_Lee format file
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* 2020-07-10 lik format file
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2022-08-14 10:29:05 +08:00
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*/
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#include "drv_spi.h"
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#ifdef RT_USING_SPI
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#ifdef BSP_USING_SPI
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//#define DRV_DEBUG
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#define LOG_TAG "drv.spi"
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#include <drv_log.h>
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#if !defined(BSP_USING_SPI0) && !defined(BSP_USING_SPI1)
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#error "Please define at least one BSP_USING_SPIx"
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/* this driver can be disabled at menuconfig ? RT-Thread Components ? Device Drivers */
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#endif
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struct swm_spi_cs
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{
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GPIO_TypeDef *GPIOx;
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uint32_t gpio_pin;
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};
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struct swm_spi_cfg
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{
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const char *name;
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SPI_TypeDef *SPIx;
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SPI_InitStructure spi_initstruct;
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};
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/* swm spi dirver class */
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struct swm_spi_device
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{
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struct swm_spi_cfg *spi_cfg;
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struct rt_spi_configuration *configure;
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struct rt_spi_bus spi_bus;
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};
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#ifdef BSP_USING_SPI0
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#ifndef SPI0_BUS_CONFIG
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#define SPI0_BUS_CONFIG \
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{ \
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.name = "spi0", \
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.SPIx = SPI0, \
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2022-08-17 00:43:24 +08:00
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.spi_initstruct.clkDiv = SPI_CLKDIV_32, \
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2022-08-14 10:29:05 +08:00
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.spi_initstruct.FrameFormat = SPI_FORMAT_SPI, \
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.spi_initstruct.SampleEdge = SPI_SECOND_EDGE, \
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.spi_initstruct.IdleLevel = SPI_HIGH_LEVEL, \
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.spi_initstruct.WordSize = 8, \
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.spi_initstruct.Master = 1, \
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2022-08-17 00:43:24 +08:00
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.spi_initstruct.RXHFullIEn = 0, \
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.spi_initstruct.TXEmptyIEn = 0, \
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2022-08-14 10:29:05 +08:00
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.spi_initstruct.TXCompleteIEn = 0, \
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}
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#endif /* SPI0_BUS_CONFIG */
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#endif /* BSP_USING_SPI0 */
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#ifdef BSP_USING_SPI1
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#ifndef SPI1_BUS_CONFIG
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#define SPI1_BUS_CONFIG \
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{ \
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.name = "spi1", \
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.SPIx = SPI1, \
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2022-08-17 00:43:24 +08:00
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.spi_initstruct.clkDiv = SPI_CLKDIV_32, \
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2022-08-14 10:29:05 +08:00
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.spi_initstruct.FrameFormat = SPI_FORMAT_SPI, \
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.spi_initstruct.SampleEdge = SPI_SECOND_EDGE, \
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.spi_initstruct.IdleLevel = SPI_HIGH_LEVEL, \
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.spi_initstruct.WordSize = 8, \
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.spi_initstruct.Master = 1, \
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2022-08-17 00:43:24 +08:00
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.spi_initstruct.RXHFullIEn = 0, \
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.spi_initstruct.TXEmptyIEn = 0, \
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2022-08-14 10:29:05 +08:00
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.spi_initstruct.TXCompleteIEn = 0, \
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}
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#endif /* SPI1_BUS_CONFIG */
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#endif /* BSP_USING_SPI1 */
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static struct swm_spi_cfg swm_spi_cfg[] =
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{
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#ifdef BSP_USING_SPI0
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SPI0_BUS_CONFIG,
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#endif
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#ifdef BSP_USING_SPI1
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SPI1_BUS_CONFIG,
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#endif
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};
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static struct swm_spi_device spi_bus_obj[sizeof(swm_spi_cfg) / sizeof(swm_spi_cfg[0])] = {0};
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static rt_err_t swm_spi_configure(struct rt_spi_device *device,
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struct rt_spi_configuration *configure)
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{
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RT_ASSERT(device != RT_NULL);
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RT_ASSERT(configure != RT_NULL);
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struct swm_spi_device *spi_drv = rt_container_of(device->bus, struct swm_spi_device, spi_bus);
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spi_drv->configure = configure;
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struct swm_spi_cfg *spi_cfg = spi_drv->spi_cfg;
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if (configure->mode & RT_SPI_SLAVE)
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{
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spi_cfg->spi_initstruct.Master = 0;
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}
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else
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{
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spi_cfg->spi_initstruct.Master = 1;
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}
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if (configure->mode & RT_SPI_3WIRE)
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{
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2023-03-16 12:44:05 +08:00
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return -RT_EINVAL;
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2022-08-14 10:29:05 +08:00
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}
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if (configure->data_width == 8)
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{
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spi_cfg->spi_initstruct.WordSize = 8;
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}
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else if (configure->data_width == 16)
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{
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spi_cfg->spi_initstruct.WordSize = 16;
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}
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else
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{
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2023-03-17 01:12:51 +08:00
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return -RT_EIO;
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2022-08-14 10:29:05 +08:00
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}
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if (configure->mode & RT_SPI_CPHA)
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{
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spi_cfg->spi_initstruct.SampleEdge = SPI_SECOND_EDGE;
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}
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else
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{
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spi_cfg->spi_initstruct.SampleEdge = SPI_FIRST_EDGE;
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}
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if (configure->mode & RT_SPI_CPOL)
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{
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spi_cfg->spi_initstruct.IdleLevel = SPI_HIGH_LEVEL;
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}
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else
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{
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spi_cfg->spi_initstruct.IdleLevel = SPI_LOW_LEVEL;
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}
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2022-08-17 00:43:24 +08:00
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if (configure->max_hz >= SystemCoreClock / 4)
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2022-08-14 10:29:05 +08:00
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{
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spi_cfg->spi_initstruct.clkDiv = SPI_CLKDIV_4;
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}
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else if (configure->max_hz >= SystemCoreClock / 8)
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{
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spi_cfg->spi_initstruct.clkDiv = SPI_CLKDIV_8;
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}
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else if (configure->max_hz >= SystemCoreClock / 16)
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{
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spi_cfg->spi_initstruct.clkDiv = SPI_CLKDIV_16;
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}
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else if (configure->max_hz >= SystemCoreClock / 32)
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{
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spi_cfg->spi_initstruct.clkDiv = SPI_CLKDIV_32;
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}
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else if (configure->max_hz >= SystemCoreClock / 64)
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{
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spi_cfg->spi_initstruct.clkDiv = SPI_CLKDIV_64;
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}
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else if (configure->max_hz >= SystemCoreClock / 128)
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{
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spi_cfg->spi_initstruct.clkDiv = SPI_CLKDIV_128;
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}
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else if (configure->max_hz >= SystemCoreClock / 256)
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{
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spi_cfg->spi_initstruct.clkDiv = SPI_CLKDIV_256;
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}
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else
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{
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/* min prescaler 512 */
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spi_cfg->spi_initstruct.clkDiv = SPI_CLKDIV_512;
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}
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SPI_Init(spi_cfg->SPIx, &(spi_cfg->spi_initstruct));
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SPI_Open(spi_cfg->SPIx);
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LOG_D("%s init done", spi_cfg->name);
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return RT_EOK;
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}
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#define SPISTEP(datalen) (((datalen) == 8) ? 1 : 2)
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#define SPISEND_1(reg, ptr, datalen) \
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do \
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{ \
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if (datalen == 8) \
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{ \
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(reg) = *(rt_uint8_t *)(ptr); \
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} \
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else \
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{ \
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(reg) = *(rt_uint16_t *)(ptr); \
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} \
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} while (0)
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#define SPIRECV_1(reg, ptr, datalen) \
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do \
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{ \
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if (datalen == 8) \
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{ \
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*(rt_uint8_t *)(ptr) = (reg); \
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} \
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else \
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{ \
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*(rt_uint16_t *)(ptr) = reg; \
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} \
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} while (0)
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static rt_err_t swm_spi_txrx1b(struct swm_spi_device *spi_drv, void *rcvb, const void *sndb)
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{
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rt_uint32_t padrcv = 0;
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rt_uint32_t padsnd = 0xFF;
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if (!rcvb && !sndb)
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{
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2023-03-17 12:12:16 +08:00
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return -RT_ERROR;
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2022-08-14 10:29:05 +08:00
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}
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if (!rcvb)
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{
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rcvb = &padrcv;
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}
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if (!sndb)
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{
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sndb = &padsnd;
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}
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while (SPI_IsTXFull(spi_drv->spi_cfg->SPIx))
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;
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SPISEND_1(spi_drv->spi_cfg->SPIx->DATA, sndb, spi_drv->spi_cfg->spi_initstruct.WordSize);
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while (SPI_IsRXEmpty(spi_drv->spi_cfg->SPIx))
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;
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SPIRECV_1(spi_drv->spi_cfg->SPIx->DATA, rcvb, spi_drv->spi_cfg->spi_initstruct.WordSize);
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return RT_EOK;
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}
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static rt_uint32_t swm_spi_xfer(struct rt_spi_device *device, struct rt_spi_message *message)
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{
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rt_err_t res;
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RT_ASSERT(device != RT_NULL);
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RT_ASSERT(device->bus != RT_NULL);
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RT_ASSERT(device->bus->parent.user_data != RT_NULL);
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RT_ASSERT(message != RT_NULL);
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struct swm_spi_device *spi_drv = rt_container_of(device->bus, struct swm_spi_device, spi_bus);
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struct swm_spi_cfg *spi_cfg = spi_drv->spi_cfg;
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struct swm_spi_cs *cs = device->parent.user_data;
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if (message->cs_take)
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{
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GPIO_ClrBit(cs->GPIOx, cs->gpio_pin);
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}
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LOG_D("%s transfer prepare and start", spi_cfg->name);
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LOG_D("%s sendbuf: %X, recvbuf: %X, length: %d",
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spi_cfg->name, (uint32_t)message->send_buf, (uint32_t)message->recv_buf, message->length);
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const rt_uint8_t *sndb = message->send_buf;
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rt_uint8_t *rcvb = message->recv_buf;
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rt_int32_t length = message->length;
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while (length)
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{
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res = swm_spi_txrx1b(spi_drv, rcvb, sndb);
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if (rcvb)
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{
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rcvb += SPISTEP(spi_cfg->spi_initstruct.WordSize);
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}
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if (sndb)
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{
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sndb += SPISTEP(spi_cfg->spi_initstruct.WordSize);
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}
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if (res != RT_EOK)
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{
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break;
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}
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length--;
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}
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/* Wait until Busy flag is reset before disabling SPI */
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while (!SPI_IsTXEmpty(spi_cfg->SPIx) && !SPI_IsRXEmpty(spi_cfg->SPIx))
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;
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if (message->cs_release)
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{
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GPIO_SetBit(cs->GPIOx, cs->gpio_pin);
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}
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return message->length - length;
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}
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const static struct rt_spi_ops swm_spi_ops =
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{
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.configure = swm_spi_configure,
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.xfer = swm_spi_xfer,
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};
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//cannot be used before completion init
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rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, GPIO_TypeDef *cs_gpiox, uint32_t cs_gpio_pin)
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{
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RT_ASSERT(bus_name != RT_NULL);
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RT_ASSERT(device_name != RT_NULL);
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rt_err_t result;
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struct rt_spi_device *spi_device;
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struct swm_spi_cs *cs_pin;
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2022-08-17 00:43:24 +08:00
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GPIO_Init(cs_gpiox, cs_gpio_pin, 1, 0, 0);
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2022-08-14 10:29:05 +08:00
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GPIO_SetBit(cs_gpiox, cs_gpio_pin);
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spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device));
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RT_ASSERT(spi_device != RT_NULL);
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cs_pin = (struct swm_spi_cs *)rt_malloc(sizeof(struct swm_spi_cs));
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RT_ASSERT(cs_pin != RT_NULL);
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cs_pin->GPIOx = cs_gpiox;
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cs_pin->gpio_pin = cs_gpio_pin;
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result = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin);
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if (result != RT_EOK)
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{
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LOG_E("%s attach to %s faild, %d\n", device_name, bus_name, result);
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}
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RT_ASSERT(result == RT_EOK);
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LOG_D("%s attach to %s done", device_name, bus_name);
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return result;
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}
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int swm_spi_init(void)
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{
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rt_err_t result;
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#ifdef BSP_USING_SPI0
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2022-08-17 00:43:24 +08:00
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PORT_Init(PORTP, PIN23, FUNMUX1_SPI0_SCLK, 0);
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PORT_Init(PORTP, PIN18, FUNMUX0_SPI0_MOSI, 0);
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PORT_Init(PORTP, PIN19, FUNMUX1_SPI0_MISO, 1);
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2022-08-14 10:29:05 +08:00
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#endif //BSP_USING_SPI0
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#ifdef BSP_USING_SPI1
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2022-08-17 00:43:24 +08:00
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PORT_Init(PORTB, PIN1, FUNMUX1_SPI1_SCLK, 0);
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PORT_Init(PORTB, PIN2, FUNMUX0_SPI1_MOSI, 0);
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PORT_Init(PORTB, PIN3, FUNMUX1_SPI1_MISO, 1);
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2022-08-14 10:29:05 +08:00
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#endif //BSP_USING_SPI1
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for (int i = 0; i < sizeof(swm_spi_cfg) / sizeof(swm_spi_cfg[0]); i++)
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{
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spi_bus_obj[i].spi_cfg = &swm_spi_cfg[i];
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spi_bus_obj[i].spi_bus.parent.user_data = &swm_spi_cfg[i];
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result = rt_spi_bus_register(&spi_bus_obj[i].spi_bus, swm_spi_cfg[i].name, &swm_spi_ops);
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if (result != RT_EOK)
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{
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LOG_E("%s bus register fail.", swm_spi_cfg[i].name);
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}
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else
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{
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LOG_D("%s bus register success.", swm_spi_cfg[i].name);
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}
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}
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return result;
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}
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INIT_BOARD_EXPORT(swm_spi_init);
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#endif /* BSP_USING_SPI */
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#endif /* RT_USING_SPI */
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