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820dd5009b
Synopsys ARCv3 ISA includes 32-bit ARC HS5x targets and 64-bit ARC HS6x targets. Both CPU families are placed in "arc64" subdirectories as it done for GCC port. Target name arc64 is used for historical reasons and Synopsys ARCv3 baremetal toolchains contain multilib configurations both for 32-bit and 64-bit families. arc32 target name is reserved for 32-bit ARC HS5x targets in case of non-multilib 32-bit builds. Note that libgloss libraries for ARCv3 are compatible with libgloss for ARCv1/2. Thus, Makefile.inc for libgloss uses sources from libgloss/arc directory except crtX.S files. Co-authored-by: Shahab Vahedi <list@vahedi.org> Co-authored-by: Claudiu Zissulescu <claziss@gmail.com> Co-authored-by: Bruno Mauricio <brunoasmauricio@gmail.com> Co-authored-by: Luis Silva <luis.m.silva99@hotmail.com> Signed-off-by: Yuriy Kolerov <ykolerov@synopsys.com>
185 lines
4.3 KiB
ArmAsm
185 lines
4.3 KiB
ArmAsm
/*
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Copyright (c) 2024, Synopsys, Inc. All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1) Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2) Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3) Neither the name of the Synopsys, Inc., nor the names of its contributors
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may be used to endorse or promote products derived from this software
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without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/asm.h>
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; This file contains variants of the same function with different
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; instructions. The generic one, the implementation that comes the
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; last after the #else macro, is the most commented.
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; Using 128-bit memory operations
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#if defined (__ARC64_M128__)
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ENTRY (memset)
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;; Assemble 128b token
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bmsk_s r1, r1, 7
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lsl8 r3, r1
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or_s r1, r1, r3
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lsl16 r3, r1
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or r6, r1, r3
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addhl r6, r6, r6
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movl r7, r6
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lsrl.f r5, r2, 6
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beq.d @.L_write_63_bytes
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movl r4, r0
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.L_write_64_bytes:
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stdl.ab r6r7, [r4, +16]
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stdl.ab r6r7, [r4, +16]
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stdl.ab r6r7, [r4, +16]
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dbnz.d r5, @.L_write_64_bytes
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stdl.ab r6r7, [r4, +16]
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bmsk_s r2, r2, 5
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.L_write_63_bytes:
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bbit0.d r2, 3, @1f
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lsr r3, r2, 4
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stl.ab r6, [r4, 8]
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1:
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bbit0.d r2, 2, @1f
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xor r3, r3, 3
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st.ab r6, [r4, 4]
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1:
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bbit0 r2, 1, @1f
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sth.ab r6, [r4, 2]
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1:
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bbit0 r2, 0, @1f
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stb.ab r6, [r4, 1]
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1:
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bi [r3]
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stdl.ab r6r7,[r4, 16]
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stdl.ab r6r7,[r4, 16]
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stdl.ab r6r7,[r4, 16]
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j_s [blink]
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.L_write_1_bytes:
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breq r2, 0, @.L_return
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dbnz.d r2, @.
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stb.ab r1, [r4, +1]
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.L_return:
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j_s [blink]
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ENDFUNC (memset)
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; The generic 64-bit implementation without any frills.
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#elif defined (__ARC64_ARCH64__) || defined (__ARC64_LL64__)
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#if defined (__ARC64_ARCH32__)
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# define MOVH mov r7,r6
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#elif defined (__ARC64_ARCH64__)
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# define MOVH addhl r6,r6,r6
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#else
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# error Please use either 32-bit or 64-bit version of arc64 compiler
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#endif
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; R0: dest
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; R1: ch
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; R2: count
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; ret (R0): dest
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ENTRY (memset)
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;; Assemble the bytes to 64bit words
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bmsk_s r1, r1, 7 ; treat it like unsigned char
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lsl8 r3, r1
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or_s r1, r1, r3
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lsl16 r3, r1
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or r6, r1, r3
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MOVH
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LSRP.f r5, r2, 5 ; counter for 32-byte chunks
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beq.d @.L_write_31_bytes
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MOVP r4, r0 ; work on a copy of "r0"
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.L_write_32_bytes:
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ST64.ab r6, [r4, +8]
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ST64.ab r6, [r4, +8]
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ST64.ab r6, [r4, +8]
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dbnz.d r5, @.L_write_32_bytes
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ST64.ab r6, [r4, +8]
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bmsk_s r2, r2, 4
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.L_write_31_bytes:
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bbit0.d r2, 2, @1f
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lsr r3, r2, 3
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st.ab r6, [r4, 4]
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1:
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bbit0.d r2, 1, @1f
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xor r3, r3, 3
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sth.ab r6, [r4, 2]
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1:
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bbit0 r2, 0, @1f
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stb.ab r6, [r4, 1]
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1:
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bi [r3]
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ST64.ab r6,[r4, 8]
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ST64.ab r6,[r4, 8]
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ST64.ab r6,[r4, 8]
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j_s [blink]
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ENDFUNC (memset)
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#elif defined (__ARC64_ARCH32__)
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ENTRY (memset)
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;; Assemble the bytes to 32bit words
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bmsk_s r1, r1, 7 ; treat it like unsigned char
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lsl8 r3, r1
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or_s r1, r1, r3
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lsl16 r3, r1
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or r6, r1, r3
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lsr.f r5, r2, 4 ; counter for 16-byte chunks
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beq.d @.L_write_15_bytes
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mov r4, r0 ; work on a copy of "r0"
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.L_write_16_bytes:
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st.ab r6, [r4, 4]
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st.ab r6, [r4, 4]
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st.ab r6, [r4, 4]
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dbnz.d r5, @.L_write_16_bytes
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st.ab r6, [r4, 4]
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bmsk_s r2, r2, 3
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.L_write_15_bytes:
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bbit0.d r2, 1, @1f
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lsr r3, r2, 2
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sth.ab r6, [r4, 2]
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1:
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bbit0.d r2, 0, @1f
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xor r3, r3, 3
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stb.ab r6, [r4, 1]
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1:
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bi [r3]
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st.ab r6,[r4, 4]
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st.ab r6,[r4, 4]
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st.ab r6,[r4, 4]
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j_s [blink]
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ENDFUNC (memset)
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#else
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# error Unknown configuration
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#endif
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