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820dd5009b
Synopsys ARCv3 ISA includes 32-bit ARC HS5x targets and 64-bit ARC HS6x targets. Both CPU families are placed in "arc64" subdirectories as it done for GCC port. Target name arc64 is used for historical reasons and Synopsys ARCv3 baremetal toolchains contain multilib configurations both for 32-bit and 64-bit families. arc32 target name is reserved for 32-bit ARC HS5x targets in case of non-multilib 32-bit builds. Note that libgloss libraries for ARCv3 are compatible with libgloss for ARCv1/2. Thus, Makefile.inc for libgloss uses sources from libgloss/arc directory except crtX.S files. Co-authored-by: Shahab Vahedi <list@vahedi.org> Co-authored-by: Claudiu Zissulescu <claziss@gmail.com> Co-authored-by: Bruno Mauricio <brunoasmauricio@gmail.com> Co-authored-by: Luis Silva <luis.m.silva99@hotmail.com> Signed-off-by: Yuriy Kolerov <ykolerov@synopsys.com>
372 lines
9.5 KiB
ArmAsm
372 lines
9.5 KiB
ArmAsm
/*
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Copyright (c) 2024, Synopsys, Inc. All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1) Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2) Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3) Neither the name of the Synopsys, Inc., nor the names of its contributors
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may be used to endorse or promote products derived from this software
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without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/asm.h>
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; r0 void* ptr
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; r1 int ch
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; r2 size_t count
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#if defined (__ARC64_ARCH32__)
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ENTRY (memchr)
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LSRP.f 0, r2, 4 ; counter for 16-byte chunks
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beq.d @.L_start_1_byte_search
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; Filter for 1 byte
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bmsk r1, r1, 7
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lsl8 r9, r1
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or r9, r9, r1
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vpack2hl r1, r9, r9
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; r1 is now setup with the special 4 byte repetition of the target byte
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; We use r1 because we dont have any more registers free inside the main loop
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; r9 can be repurposed
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mov r8, NULL_32DT_1
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ror r9, r8
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xor r3, r3, r3
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.L_search_16_bytes:
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#if defined (__ARC64_LL64__)
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ldd.ab r4r5, [r0, +8]
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ldd.ab r6r7, [r0, +8]
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#else
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ld.ab r4, [r0, +4]
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ld.ab r5, [r0, +4]
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ld.ab r6, [r0, +4]
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ld.ab r7, [r0, +4]
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#endif
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xor r4, r4, r1
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xor r5, r5, r1
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xor r6, r6, r1
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xor r7, r7, r1
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sub r10, r4, r8
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sub r11, r5, r8
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sub r12, r6, r8
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sub r13, r7, r8
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bic r10, r10, r4
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bic r11, r11, r5
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bic r12, r12, r6
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bic r13, r13, r7
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tst r10, r9
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bset.ne r3, r3, 4
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tst r11, r9
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bset.ne r3, r3, 3
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tst r12, r9
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bset.ne r3, r3, 2
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tst r13, r9
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bset.ne r3, r3, 1
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; Break if found
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brne.d r3, 0, @.L_found_in_16B
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; Keep going we have more 16 byte chunks
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sub r2, r2, 16
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brge r2, 16, @.L_search_16_bytes
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; Reset byte repetition of r1 to 1 single byte
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bmsk r1, r1, 7
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.L_start_1_byte_search:
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; Check if r2 is 0
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breq.d r2, 0, @.L_byte_not_found
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ldb.ab r10, [r0, +1]
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.L_search_1_byte:
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breq r10, r1, @.L_found_byte
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dbnz.d r2, @.L_search_1_byte
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ldb.ab r10, [r0, +1]
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; Byte not found
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.L_byte_not_found:
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j.d [blink]
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MOVP r0, 0
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.L_found_byte:
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j_s.d [blink]
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SUBP r0, r0, 1
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.L_found_in_16B:
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fls r5, r3 ; [2]
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; Select appropriate register to analyze [4]
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mov r2, r13
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; Point r13 to first NULL byte containing double word [3]
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sub2 r0, r0, r5
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asr.f r3, r3, 3
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mov.c r2, r12
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asr.f r3, r3, 1
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mov.c r2, r11
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asr.f r3, r3, 1
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mov.c r2, r10
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and r2, r2, r9 ; [5]
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ffs r2, r2 ; [6]
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xbfu r2, r2, 0b0111000011 ; [7]
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j.d [blink]
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add r0, r0, r2 ; [8]
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ENDFUNC (memchr)
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#else
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ENTRY (memchr)
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lsrl.f 0, r2, 5 ; counter for 32-byte chunks
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beq.d @.L_start_1_byte_search
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; Filter for 1 byte
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bmsk r1, r1, 7
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lsl8 r9, r1
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or r9, r9, r1
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vpack2hl r1, r9, r9
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vpack2wl r1, r1, r1
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; r1 is now setup with the special 4 byte repetition of the target byte
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; We use r1 because we dont have any more registers free inside the main loop
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; r9 can be repurposed
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vpack2wl r8, NULL_32DT_1, NULL_32DT_1
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asll r9, r8, 7
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xorl r3, r3, r3
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.L_search_32_bytes:
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; Using 128-bit memory operations
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#if defined (__ARC64_M128__)
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lddl.ab r4r5, [r0, +16]
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lddl.ab r6r7, [r0, +16]
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; The 64-bit crunching implementation.
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#elif defined (__ARC64_ARCH64__)
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ldl.ab r4, [r0, +8]
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ldl.ab r5, [r0, +8]
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ldl.ab r6, [r0, +8]
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ldl.ab r7, [r0, +8]
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#else
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# error Unknown configuration
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#endif
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xorl r4, r4, r1
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xorl r5, r5, r1
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xorl r6, r6, r1
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xorl r7, r7, r1
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subl r10, r4, r8
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subl r11, r5, r8
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subl r12, r6, r8
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subl r13, r7, r8
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bicl r10, r10, r4
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bicl r11, r11, r5
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bicl r12, r12, r6
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bicl r13, r13, r7
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tstl r10, r9
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bset.ne r3, r3, 4
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tstl r11, r9
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bset.ne r3, r3, 3
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tstl r12, r9
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bset.ne r3, r3, 2
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tstl r13, r9
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bset.ne r3, r3, 1
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; Break if found
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brne.d r3, 0, @.L_found_in_32B
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; Keep going we have more 16 byte chunks
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subl r2, r2, 32
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brge r2, 32, @.L_search_32_bytes
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; Reset byte repetition of r1 to 1 single byte
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bmskl r1, r1, 7
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.L_start_1_byte_search:
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; Check if r2 is 0
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breq.d r2, 0, @.L_byte_not_found
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ldb.ab r10, [r0, +1]
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.L_search_1_byte:
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breq r10, r1, @.L_found_byte
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dbnz.d r2, @.L_search_1_byte
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ldb.ab r10, [r0, +1]
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; Byte not found
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.L_byte_not_found:
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j.d [blink]
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movl r0, 0
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.L_found_byte:
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j_s.d [blink]
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subl r0, r0, 1
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.L_found_in_32B:
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fls r5, r3 ; [2]
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; Select appropriate register to analyze [4]
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movl r2, r13
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; Point r13 to first NULL byte containing double word [3]
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sub3l r0, r0, r5
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asr.f r3, r3, 3
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movl.c r2, r12
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asr.f r3, r3, 1
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movl.c r2, r11
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asr.f r3, r3, 1
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movl.c r2, r10
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andl r2, r2, r9 ; [5]
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ffsl r2, r2 ; [6]
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xbful r2, r2, 0b0111000011 ; [7]
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j.d [blink]
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addl r0, r0, r2 ; [8]
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ENDFUNC (memchr)
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#endif
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;; This code uses a common technique for NULL byte detection inside a word.
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;; Details on this technique can be found in:
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;; (https://graphics.stanford.edu/~seander/bithacks.html#ZeroInWord)
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;
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; In sum, this technique allows for detecting a NULL byte inside any given
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; amount of bits by performing the following operation
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; DETECTNULL(X) (((X) - 0x01010101) & ~(X) & 0x80808080) [0]
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;
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; The code above implements this by setting r8 to a 0x01010101... sequence and
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; r9 to a 0x80808080... sequence of appropriate length
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; As LIMM are 32 bit only, we need to perform MOVHL and ORL [1] operations to
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; have the appropriate 64 bit values in place
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;
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; As we want a specific byte and not a NULL byte, we create in r1 a constant
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; that is made up of the target byte, on each byte position, that we xor with
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; the loaded data to force a NULL byte only if the target byte is present.
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; After that we can use the technique directly
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;
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;; Search is done 32 bytes at a time, either with 64 bit loads or 128 bit loads
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;; If the target byte is detected, the position of the double word is encoded
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;; in r3, which is eventually used to adjust r0
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;
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; r3 is set via bset, which means we can simply use a fls to obtain the first
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; match (or ffs depending on the values in bset) [2].
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; The reason for starting at 1 and not 0 is so r3 encodes how many double
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; words to go back, and it wouldnt make sense to go back 0 (the byte would be
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; in the next loop iteration).
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;
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; The first step to take is point r0 to the appropriate double word.
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; As the chosen encoded information is how many double words to go back,
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; we can simply multiply r3 by 8 and reduce r0 by that amount [3]
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;
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; Then, we need to place the loaded double word containing the first target byte
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; found, into a "common" register we can operate on later [4].
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;
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; To do this without any jumps, we can shift r3 and perform a conditional mov
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; based on the carry flag value.
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; The order is very important because the byte can appear in several double
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; words, so we want to analyze from last to first.
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;
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; We can ignore the first asr (which would be asr.f 2, as we started r3 on 1)
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; because if r13 isnt the target byte, r2 will always be overwritten so we can
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; just decide to start at r7, and overwrite it if needed.
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;
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; Now comes the tricky part. In order to obtain the first target byte, we need
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; to understand the NULL byte detection operation. It is explained in depth in
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; the link above but in short, it works by first setting the highest bit of each
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; byte to 1, if the corresponding byte is either 0 or more than 0x80
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; Then, separately, it makes the highest bit of each byte 1, if the byte is
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; less than 0x80. The last step is to AND these two values (this operation is
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; simplified with the SUB, BIC and TST instructions).
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;
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; This means that the evaluated equation result value [5] has zeros for all non
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; zero bytes, except for the NULL bytes (which are the target bytes after the
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; xor). Therefore, we can simply find the first non zero bit (counting from bit
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; 0) which will be inside the position of the first NULL byte.
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;
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; One thing to note, is that ffs oddly returns 31 if no bit is found, setting
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; the zero flag. As r9 is never all 0s at this stage (would mean there is no
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; NULL byte and we wouldnt be here) we dont need to worry about that. [6]
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;
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; We can then convert the bit position into the last byte position by looking
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; into bits 3 to 5, and shifting 3 bits to the right. This can be combined into
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; a single xbful operation. The bottom 000011 represent shift by 3 and the top
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; 0111 represents the mask (3 to 5 shifted by 3 is 0 to 2). We dont need to
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; worry about the case where ffs does not find a bit, because we know for sure
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; there is at least one NULL byte, and therefore one of the highest bits is set
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; to 1 [7]
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;
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; Finally, we can add the NULL/target byte position inside the loaded double
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; word to r0 to obtain the bytes absolute position [8]
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;
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;
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; Some operations are re-ordered such that register dependency is reduced,
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; allowing the CPU to run more instructions in parallel
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;
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