197 lines
6.2 KiB
Plaintext
197 lines
6.2 KiB
Plaintext
2005-01-21 Fred Fish <fnf@specifixinc.com>
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* mips.h: Change INSN_ALIAS to INSN2_ALIAS.
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Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
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Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
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2005-01-19 Fred Fish <fnf@specifixinc.com>
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* mips.h (struct mips_opcode): Add new pinfo2 member.
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(INSN_ALIAS): New define for opcode table entries that are
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specific instances of another entry, such as 'move' for an 'or'
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with a zero operand.
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(INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
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(INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
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2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
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* mips.h (CPU_RM9000): Define.
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(OPCODE_IS_MEMBER): Handle CPU_RM9000.
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2004-11-25 Jan Beulich <jbeulich@novell.com>
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* i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
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to/from test registers are illegal in 64-bit mode. Add missing
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NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
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(previously one had to explicitly encode a rex64 prefix). Re-enable
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lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
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support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
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2004-11-23 Jan Beulich <jbeulich@novell.com>
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* i386.h (i386_optab): paddq and psubq, even in their MMX form, are
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available only with SSE2. Change the MMX additions introduced by SSE
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and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
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instructions by their now designated identifier (since combining i686
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and 3DNow! does not really imply 3DNow!A).
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2004-11-19 Alan Modra <amodra@bigpond.net.au>
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* msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
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struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
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2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
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Vineet Sharma <vineets@noida.hcltech.com>
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* maxq.h: New file: Disassembly information for the maxq port.
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2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
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* i386.h (i386_optab): Put back "movzb".
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2004-11-04 Hans-Peter Nilsson <hp@axis.com>
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* cris.h (enum cris_insn_version_usage): Tweak formatting and
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comments. Remove member cris_ver_sim. Add members
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cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
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cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
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(struct cris_support_reg, struct cris_cond15): New types.
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(cris_conds15): Declare.
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(JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
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(NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
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(NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
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(NOP_Z_BITS): Define in terms of NOP_OPCODE.
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(cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
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SIZE_FIELD_UNSIGNED.
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2004-11-04 Jan Beulich <jbeulich@novell.com>
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* i386.h (sldx_Suf): Remove.
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(FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
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(q_FP): Define, implying no REX64.
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(x_FP, sl_FP): Imply FloatMF.
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(i386_optab): Split reg and mem forms of moving from segment registers
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so that the memory forms can ignore the 16-/32-bit operand size
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distinction. Adjust a few others for Intel mode. Remove *FP uses from
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all non-floating-point instructions. Unite 32- and 64-bit forms of
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movsx, movzx, and movd. Adjust floating point operations for the above
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changes to the *FP macros. Add DefaultSize to floating point control
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insns operating on larger memory ranges. Remove left over comments
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hinting at certain insns being Intel-syntax ones where the ones
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actually meant are already gone.
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2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
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* crx.h: Add COPS_REG_INS - Coprocessor Special register
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instruction type.
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2004-09-30 Paul Brook <paul@codesourcery.com>
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* arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
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(ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
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2004-09-11 Theodore A. Roth <troth@openavr.org>
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* avr.h: Add support for
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atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
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2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
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* ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
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2004-08-24 Dmitry Diky <diwil@spec.ru>
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* msp430.h (msp430_opc): Add new instructions.
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(msp430_rcodes): Declare new instructions.
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(msp430_hcodes): Likewise..
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2004-08-13 Nick Clifton <nickc@redhat.com>
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PR/301
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* h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
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processors.
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2004-08-30 Michal Ludvig <mludvig@suse.cz>
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* i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
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2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
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* i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
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2004-07-21 Jan Beulich <jbeulich@novell.com>
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* i386.h: Adjust instruction descriptions to better match the
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specification.
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2004-07-16 Richard Earnshaw <rearnsha@arm.com>
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* arm.h: Remove all old content. Replace with architecture defines
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from gas/config/tc-arm.c.
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2004-07-09 Andreas Schwab <schwab@suse.de>
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* m68k.h: Fix comment.
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2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
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* crx.h: New file.
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2004-06-24 Alan Modra <amodra@bigpond.net.au>
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* i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
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2004-05-24 Peter Barada <peter@the-baradas.com>
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* m68k.h: Add 'size' to m68k_opcode.
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2004-05-05 Peter Barada <peter@the-baradas.com>
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* m68k.h: Switch from ColdFire chip name to core variant.
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2004-04-22 Peter Barada <peter@the-baradas.com>
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* m68k.h: Add mcfmac/mcfemac definitions. Update operand
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descriptions for new EMAC cases.
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Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
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handle Motorola MAC syntax.
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Allow disassembly of ColdFire V4e object files.
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2004-03-16 Alan Modra <amodra@bigpond.net.au>
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* ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
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2004-03-12 Jakub Jelinek <jakub@redhat.com>
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* i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
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2004-03-12 Michal Ludvig <mludvig@suse.cz>
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* i386.h (i386_optab): Added xstore as an alias for xstorerng.
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2004-03-12 Michal Ludvig <mludvig@suse.cz>
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* i386.h (i386_optab): Added xstore/xcrypt insns.
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2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
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* h8300.h (32bit ldc/stc): Add relaxing support.
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2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
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* h8300.h (BITOP): Pass MEMRELAX flag.
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2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
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* h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
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except for the H8S.
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For older changes see ChangeLog-9103
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Local Variables:
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mode: change-log
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left-margin: 8
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fill-column: 74
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version-control: never
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End:
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