449 lines
14 KiB
C++
Executable File
449 lines
14 KiB
C++
Executable File
/* fenv.cc
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Copyright 2010, 2011 Red Hat, Inc.
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This file is part of Cygwin.
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This software is a copyrighted work licensed under the terms of the
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Cygwin license. Please consult the file "CYGWIN_LICENSE" for
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details. */
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#include "winsup.h"
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#include "fenv.h"
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#include "errno.h"
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#include "wincap.h"
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#include <string.h>
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/* Mask and shift amount for rounding bits. */
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#define FE_CW_ROUND_MASK (0x0c00)
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#define FE_CW_ROUND_SHIFT (10)
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/* Same, for SSE MXCSR. */
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#define FE_MXCSR_ROUND_MASK (0x6000)
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#define FE_MXCSR_ROUND_SHIFT (13)
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/* Mask and shift amount for precision bits. */
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#define FE_CW_PREC_MASK (0x0300)
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#define FE_CW_PREC_SHIFT (8)
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/* In x87, exception status bits and mask bits occupy
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corresponding bit positions in the status and control
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registers, respectively. In SSE, they are both located
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in the control-and-status register, with the status bits
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corresponding to the x87 positions, and the mask bits
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shifted by this amount to the left. */
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#define FE_SSE_EXCEPT_MASK_SHIFT (7)
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/* These are writable so we can initialise them at startup. */
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static fenv_t fe_dfl_env;
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static fenv_t fe_nomask_env;
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/* These pointers provide the outside world with read-only access to them. */
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const fenv_t *_fe_dfl_env = &fe_dfl_env;
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const fenv_t *_fe_nomask_env = &fe_nomask_env;
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/* Although Cygwin assumes i686 or above (hence SSE available) these
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days, and the compiler feels free to use it (depending on compile-
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time flags of course), we should avoid needlessly breaking any
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purely integer mode apps (or apps compiled with -mno-sse), so we
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only manage SSE state in this fenv module if we detect that SSE
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instructions are available at runtime. If we didn't do this, all
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applications run on older machines would bomb out with an invalid
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instruction exception right at startup; let's not be *that* WJM! */
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static bool use_sse = false;
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/* This function enables traps for each of the exceptions as indicated
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by the parameter except. The individual exceptions are described in
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[ ... glibc manual xref elided ...]. Only the specified exceptions are
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enabled, the status of the other exceptions is not changed.
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The function returns the previous enabled exceptions in case the
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operation was successful, -1 otherwise. */
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int
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feenableexcept (int excepts)
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{
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unsigned short cw, old_cw;
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unsigned int mxcsr = 0;
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if (excepts & ~FE_ALL_EXCEPT)
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return -1;
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/* Get control words. */
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__asm__ volatile ("fnstcw %0" : "=m" (old_cw) : );
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if (use_sse)
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__asm__ volatile ("stmxcsr %0" : "=m" (mxcsr) : );
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/* Enable exceptions by clearing mask bits. */
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cw = old_cw & ~excepts;
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mxcsr &= ~(excepts << FE_SSE_EXCEPT_MASK_SHIFT);
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/* Store updated control words. */
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__asm__ volatile ("fldcw %0" :: "m" (cw));
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if (use_sse)
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__asm__ volatile ("ldmxcsr %0" :: "m" (mxcsr));
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/* Return old value. We assume SSE and x87 stay in sync. Note that
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we are returning a mask of enabled exceptions, which is the opposite
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of the flags in the register, which are set to disable (mask) their
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related exceptions. */
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return (~old_cw) & FE_ALL_EXCEPT;
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}
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/* This function disables traps for each of the exceptions as indicated
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by the parameter except. The individual exceptions are described in
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[ ... glibc manual xref elided ...]. Only the specified exceptions are
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disabled, the status of the other exceptions is not changed.
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The function returns the previous enabled exceptions in case the
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operation was successful, -1 otherwise. */
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int
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fedisableexcept (int excepts)
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{
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unsigned short cw, old_cw;
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unsigned int mxcsr = 0;
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if (excepts & ~FE_ALL_EXCEPT)
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return -1;
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/* Get control words. */
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__asm__ volatile ("fnstcw %0" : "=m" (old_cw) : );
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if (use_sse)
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__asm__ volatile ("stmxcsr %0" : "=m" (mxcsr) : );
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/* Disable exceptions by setting mask bits. */
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cw = old_cw | excepts;
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mxcsr |= (excepts << FE_SSE_EXCEPT_MASK_SHIFT);
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/* Store updated control words. */
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__asm__ volatile ("fldcw %0" :: "m" (cw));
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if (use_sse)
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__asm__ volatile ("ldmxcsr %0" :: "m" (mxcsr));
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/* Return old value. We assume SSE and x87 stay in sync. Note that
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we are returning a mask of enabled exceptions, which is the opposite
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of the flags in the register, which are set to disable (mask) their
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related exceptions. */
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return (~old_cw) & FE_ALL_EXCEPT;
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}
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/* This function returns a bitmask of all currently enabled exceptions. It
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returns -1 in case of failure. */
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int
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fegetexcept (void)
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{
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unsigned short cw;
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/* Get control word. We assume SSE and x87 stay in sync. */
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__asm__ volatile ("fnstcw %0" : "=m" (cw) : );
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/* Exception is *dis*abled when mask bit is set. */
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return (~cw) & FE_ALL_EXCEPT;
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}
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/* Store the floating-point environment in the variable pointed to by envp.
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The function returns zero in case the operation was successful, a non-zero
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value otherwise. */
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int
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fegetenv (fenv_t *envp)
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{
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__asm__ volatile ("fnstenv %0" : "=m" (envp->_fpu) : );
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if (use_sse)
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__asm__ volatile ("stmxcsr %0" : "=m" (envp->_sse_mxcsr) : );
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return 0;
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}
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/* Store the current floating-point environment in the object pointed to
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by envp. Then clear all exception flags, and set the FPU to trap no
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exceptions. Not all FPUs support trapping no exceptions; if feholdexcept
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cannot set this mode, it returns nonzero value. If it succeeds, it
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returns zero. */
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int
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feholdexcept (fenv_t *envp)
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{
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unsigned int mxcsr;
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fegetenv (envp);
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mxcsr = envp->_sse_mxcsr & ~FE_ALL_EXCEPT;
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if (use_sse)
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__asm__ volatile ("ldmxcsr %0" :: "m" (mxcsr));
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__asm__ volatile ("fnclex");
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fedisableexcept (FE_ALL_EXCEPT);
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return 0;
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}
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/* Set the floating-point environment to that described by envp. The
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function returns zero in case the operation was successful, a non-zero
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value otherwise. */
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int
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fesetenv (const fenv_t *envp)
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{
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__asm__ volatile ("fldenv %0" :: "m" (envp->_fpu) );
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if (use_sse)
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__asm__ volatile ("ldmxcsr %0" :: "m" (envp->_sse_mxcsr));
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return 0;
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}
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/* Like fesetenv, this function sets the floating-point environment to
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that described by envp. However, if any exceptions were flagged in the
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status word before feupdateenv was called, they remain flagged after
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the call. In other words, after feupdateenv is called, the status
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word is the bitwise OR of the previous status word and the one saved
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in envp. The function returns zero in case the operation was successful,
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a non-zero value otherwise. */
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int
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feupdateenv (const fenv_t *envp)
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{
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fenv_t envcopy;
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unsigned int mxcsr = 0;
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unsigned short sw;
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/* Don't want to modify *envp, but want to update environment atomically,
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so take a copy and merge the existing exceptions into it. */
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memcpy (&envcopy, envp, sizeof *envp);
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__asm__ volatile ("fnstsw %0" : "=m" (sw) : );
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if (use_sse)
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__asm__ volatile ("stmxcsr %0" : "=m" (mxcsr) : );
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envcopy._fpu._fpu_sw |= (sw & FE_ALL_EXCEPT);
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envcopy._sse_mxcsr |= (mxcsr & FE_ALL_EXCEPT);
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return fesetenv (&envcopy);
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}
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/* This function clears all of the supported exception flags indicated by
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excepts. The function returns zero in case the operation was successful,
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a non-zero value otherwise. */
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int
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feclearexcept (int excepts)
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{
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fenv_t fenv;
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if (excepts & ~FE_ALL_EXCEPT)
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return EINVAL;
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/* Need to save/restore whole environment to modify status word. */
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fegetenv (&fenv);
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/* Mask undesired bits out. */
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fenv._fpu._fpu_sw &= ~excepts;
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fenv._sse_mxcsr &= ~excepts;
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/* Set back into FPU state. */
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return fesetenv (&fenv);
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}
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/* This function raises the supported exceptions indicated by
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excepts. If more than one exception bit in excepts is set the order
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in which the exceptions are raised is undefined except that overflow
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(FE_OVERFLOW) or underflow (FE_UNDERFLOW) are raised before inexact
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(FE_INEXACT). Whether for overflow or underflow the inexact exception
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is also raised is also implementation dependent. The function returns
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zero in case the operation was successful, a non-zero value otherwise. */
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int
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feraiseexcept (int excepts)
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{
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fenv_t fenv;
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if (excepts & ~FE_ALL_EXCEPT)
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return EINVAL;
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/* Need to save/restore whole environment to modify status word. */
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__asm__ volatile ("fnstenv %0" : "=m" (fenv) : );
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/* Set desired exception bits. */
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fenv._fpu._fpu_sw |= excepts;
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/* Set back into FPU state. */
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__asm__ volatile ("fldenv %0" :: "m" (fenv));
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/* And trigger them - whichever are unmasked. */
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__asm__ volatile ("fwait");
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return 0;
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}
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/* Test whether the exception flags indicated by the parameter except
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are currently set. If any of them are, a nonzero value is returned
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which specifies which exceptions are set. Otherwise the result is zero. */
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int
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fetestexcept (int excepts)
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{
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unsigned short sw;
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unsigned int mxcsr = 0;
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if (excepts & ~FE_ALL_EXCEPT)
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return EINVAL;
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/* Get status registers. */
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__asm__ volatile ("fnstsw %0" : "=m" (sw) : );
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if (use_sse)
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__asm__ volatile ("stmxcsr %0" : "=m" (mxcsr) : );
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/* Mask undesired bits out and return result. */
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return (sw | mxcsr) & excepts;
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}
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/* This function stores in the variable pointed to by flagp an
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implementation-defined value representing the current setting of the
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exception flags indicated by excepts. The function returns zero in
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case the operation was successful, a non-zero value otherwise. */
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int
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fegetexceptflag (fexcept_t *flagp, int excepts)
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{
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unsigned short sw;
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unsigned int mxcsr = 0;
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if (excepts & ~FE_ALL_EXCEPT)
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return EINVAL;
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/* Get status registers. */
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__asm__ volatile ("fnstsw %0" : "=m" (sw) : );
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if (use_sse)
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__asm__ volatile ("stmxcsr %0" : "=m" (mxcsr) : );
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/* Mask undesired bits out and set result struct. */
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flagp->_fpu_exceptions = (sw & excepts);
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flagp->_sse_exceptions = (mxcsr & excepts);
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return 0;
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}
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/* This function restores the flags for the exceptions indicated by
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excepts to the values stored in the variable pointed to by flagp. */
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int
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fesetexceptflag (const fexcept_t *flagp, int excepts)
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{
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fenv_t fenv;
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if (excepts & ~FE_ALL_EXCEPT)
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return EINVAL;
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/* Need to save/restore whole environment to modify status word. */
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fegetenv (&fenv);
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/* Set/Clear desired exception bits. */
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fenv._fpu._fpu_sw &= ~excepts;
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fenv._fpu._fpu_sw |= (excepts & flagp->_fpu_exceptions);
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fenv._sse_mxcsr &= ~excepts;
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fenv._sse_mxcsr |= (excepts & flagp->_sse_exceptions);
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/* Set back into FPU state. */
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return fesetenv (&fenv);
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}
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/* Returns the currently selected rounding mode, represented by one of the
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values of the defined rounding mode macros. */
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int
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fegetround (void)
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{
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unsigned short cw;
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/* Get control word. We assume SSE and x87 stay in sync. */
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__asm__ volatile ("fnstcw %0" : "=m" (cw) : );
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return (cw & FE_CW_ROUND_MASK) >> FE_CW_ROUND_SHIFT;
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}
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/* Changes the currently selected rounding mode to round. If round does
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not correspond to one of the supported rounding modes nothing is changed.
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fesetround returns zero if it changed the rounding mode, a nonzero value
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if the mode is not supported. */
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int
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fesetround (int round)
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{
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unsigned short cw;
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unsigned int mxcsr = 0;
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/* Will succeed for any valid value of the input parameter. */
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if (round & ~(FE_CW_ROUND_MASK >> FE_CW_PREC_SHIFT))
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return EINVAL;
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/* Get control words. */
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__asm__ volatile ("fnstcw %0" : "=m" (cw) : );
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if (use_sse)
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__asm__ volatile ("stmxcsr %0" : "=m" (mxcsr) : );
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/* Twiddle bits. */
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cw &= ~FE_CW_ROUND_MASK;
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cw |= (round << FE_CW_ROUND_SHIFT);
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mxcsr &= ~FE_MXCSR_ROUND_MASK;
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mxcsr |= (round << FE_MXCSR_ROUND_SHIFT);
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/* Set back into FPU state. */
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__asm__ volatile ("fldcw %0" :: "m" (cw));
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if (use_sse)
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__asm__ volatile ("ldmxcsr %0" :: "m" (mxcsr));
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/* Indicate success. */
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return 0;
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}
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/* Returns the currently selected precision, represented by one of the
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values of the defined precision macros. */
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int
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fegetprec (void)
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{
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unsigned short cw;
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/* Get control word. */
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__asm__ volatile ("fnstcw %0" : "=m" (cw) : );
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return (cw & FE_CW_PREC_MASK) >> FE_CW_PREC_SHIFT;
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}
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/* Changes the currently selected precision to prec. If prec does not
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correspond to one of the supported rounding modes nothing is changed.
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fesetprec returns zero if it changed the precision, or a nonzero value
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if the mode is not supported. */
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int
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fesetprec (int prec)
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{
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unsigned short cw;
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/* Will succeed for any valid value of the input parameter. */
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if (prec & ~(FE_CW_PREC_MASK >> FE_CW_PREC_SHIFT) || prec == FE_RESERVEDPREC)
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return EINVAL;
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/* Get control word. */
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__asm__ volatile ("fnstcw %0" : "=m" (cw) : );
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/* Twiddle bits. */
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cw &= ~FE_CW_PREC_MASK;
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cw |= (prec << FE_CW_PREC_SHIFT);
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/* Set back into FPU state. */
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__asm__ volatile ("fldcw %0" :: "m" (cw));
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/* Indicate success. */
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return 0;
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}
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/* Set up the FPU and SSE environment at the start of execution. */
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void
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_feinitialise (void)
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{
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unsigned int edx, eax, mxcsr;
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/* Check for presence of SSE: invoke CPUID #1, check EDX bit 25. */
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eax = 1;
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__asm__ volatile ("cpuid" : "=d" (edx), "+a" (eax) :: "%ecx", "%ebx");
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/* If this flag isn't set, or if the OS doesn't support SSE (NT4, at least
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up to SP4) we'll avoid trying to execute any SSE. */
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if ((edx & (1 << 25)) != 0 && wincap.supports_sse ())
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use_sse = true;
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/* Reset FPU: extended prec, all exceptions cleared and masked off. */
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__asm__ volatile ("fninit");
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/* The default cw value, 0x37f, is rounding mode zero. The MXCSR has
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no precision control, so the only thing to do is set the exception
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mask bits. */
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mxcsr = FE_ALL_EXCEPT << FE_SSE_EXCEPT_MASK_SHIFT;
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if (use_sse)
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__asm__ volatile ("ldmxcsr %0" :: "m" (mxcsr));
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/* Setup unmasked environment. */
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feenableexcept (FE_ALL_EXCEPT);
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fegetenv (&fe_nomask_env);
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/* Restore default exception masking (all masked). */
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fedisableexcept (FE_ALL_EXCEPT);
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/* Finally cache state as default environment. */
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fegetenv (&fe_dfl_env);
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}
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