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d4b522efa8
* gas/config/tc-arm.c (limits.h): Include.
(fpu_arch_vfp_v3, fpu_vfp_ext_v3, fpu_neon_ext_v1)
(fpu_vfp_v3_or_neon_ext): Declare constants.
(neon_el_type): New enumeration of types for Neon vector elements.
(neon_type_el): New struct. Define type and size of a vector element.
(NEON_MAX_TYPE_ELS): Define constant. The maximum number of types per
instruction.
(neon_type): Define struct. The type of an instruction.
(arm_it): Add 'vectype' for the current instruction.
(isscalar, immisalign, regisimm, isquad): New predicates for operands.
(vfp_sp_reg_pos): Rename to...
(vfp_reg_pos): ...this, and add VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
tags.
(arm_reg_type): Add REG_TYPE_NQ (Neon Q register) and REG_TYPE_NDQ
(Neon D or Q register).
(reg_expected_msgs): Sync with above. Allow VFD to mean VFP or Neon
D register.
(GE_OPT_PREFIX_BIG): Define constant, for use in...
(my_get_expression): Allow above constant as argument to accept
64-bit constants with optional prefix.
(arm_reg_parse): Add extra argument to return the specific type of
register in when either a D or Q register (REG_TYPE_NDQ) is requested.
Can be NULL.
(parse_scalar): New function. Parse Neon scalar (vector reg and index).
(parse_reg_list): Update for new arm_reg_parse args.
(parse_vfp_reg_list): Allow parsing of Neon D/Q register lists.
(parse_neon_el_struct_list): New function. Parse element/structure
register lists for VLD<n>/VST<n> instructions.
(s_arm_unwind_save_vfp): Update for new parse_vfp_reg_list args.
(s_arm_unwind_save_mmxwr): Likewise.
(s_arm_unwind_save_mmxwcg): Likewise.
(s_arm_unwind_movsp): Likewise.
(s_arm_unwind_setfp): Likewise.
(parse_big_immediate): New function. Parse an immediate, which may
be 64 bits wide. Put results in inst.operands[i].
(parse_shift): Update for new arm_reg_parse args.
(parse_address): Likewise. Add parsing of alignment specifiers.
(parse_neon_mov): Parse the operands of a VMOV instruction.
(operand_parse_code): Add OP_RND, OP_RNQ, OP_RNDQ, OP_RNSC,
OP_NRDLST, OP_NSTRLST, OP_NILO, OP_RNDQ_I0, OP_RR_RNSC,
OP_RNDQ_RNSC, OP_RND_RNSC, OP_VMOV, OP_RNDQ_IMVNb, OP_RNDQ_I63b,
OP_I0, OP_I16z, OP_I32z, OP_I64, OP_I64z, OP_oI32b, OP_oRND,
OP_oRNQ, OP_oRNDQ.
(parse_operands): Handle new codes above.
(encode_arm_vfp_sp_reg): Rename to...
(encode_arm_vfp_reg): ...this. Handle D regs (0-31) too. Complain if
selected VFP version only supports D0-D15.
(do_vfp_sp_monadic, do_vfp_sp_dyadic, do_vfp_sp_compare_z)
(do_vfp_dp_sp_cvt, do_vfp_reg_from_sp, do_vfp_reg2_from_sp2)
(do_vfp_sp_from_reg, do_vfp_sp2_from_reg2, do_vfp_sp_ldst)
(do_vfp_dp_ldst, vfp_sp_ldstm, vfp_dp_ldstm): Update for new
encode_arm_vfp_reg name, and allow 32 D regs.
(do_vfp_dp_rd_rm, do_vfp_dp_rn_rd, do_vfp_dp_rd_rn)
(do_vfp_dp_rd_rn_rm, do_vfp_rm_rd_rn): New functions to encode VFP
insns allowing 32 D regs.
(do_vfp_sp_const, do_vfp_dp_const, vfp_conv, do_vfp_sp_conv_16)
(do_vfp_dp_conv_16, do_vfp_sp_conv_32, do_vfp_dp_conv_32): Handle
constant-load and conversion insns introduced with VFPv3.
(neon_tab_entry): New struct.
(NEON_ENC_TAB): Bit patterns for overloaded Neon instructions, and
those which are the targets of pseudo-instructions.
(neon_opc): Enumerate opcodes, use as indices into...
(neon_enc_tab): ...this. Hold data from NEON_ENC_TAB.
(NEON_ENC_INTEGER, NEON_ENC_ARMREG, NEON_ENC_POLY, NEON_ENC_FLOAT)
(NEON_ENC_SCALAR, NEON_ENC_IMMED, NEON_ENC_INTERLV, NEON_ENC_LANE)
(NEON_ENC_DUP): Define meaningful helper macros to look up values in
neon_enc_tab.
(neon_shape): Enumerate shapes (permitted register widths, etc.) for
Neon instructions.
(neon_type_mask): New. Compact type representation for type
checking.
(N_SU_ALL, N_SU_32, N_SU_16_64, N_SUF_32, N_I_ALL, N_IF_32): Common
permitted type combinations.
(N_IGNORE_TYPE): New macro.
(neon_check_shape): New function. Check an instruction shape for
multiple alternatives. Return the specific shape for the current
instruction.
(neon_modify_type_size): New function. Modify a vector type and
size, depending on the bit mask in argument 1.
(neon_type_promote): New function. Convert a given "key" type (of an
operand) into the correct type for a different operand, based on a bit
mask.
(type_chk_of_el_type): New function. Convert a type and size into the
compact representation used for type checking.
(el_type_of_type_ckh): New function. Reverse of above (only when a
single bit is set in the bit mask).
(modify_types_allowed): New function. Alter a mask of allowed types
based on a bit mask of modifications.
(neon_check_type): New function. Check the type of the current
instruction against the variable argument list. The "key" type of the
instruction is returned.
(neon_dp_fixup): New function. Fill in and modify instruction bits for
a Neon data-processing instruction depending on whether we're in ARM
mode or Thumb-2 mode.
(neon_logbits): New function.
(neon_three_same, neon_two_same, do_neon_dyadic_i_su)
(do_neon_dyadic_i64_su, neon_imm_shift, do_neon_shl_imm)
(do_neon_qshl_imm, neon_cmode_for_logic_imm)
(neon_bits_same_in_bytes, neon_squash_bits, neon_is_quarter_float)
(neon_qfloat_bits, neon_cmode_for_move_imm, neon_write_immbits)
(neon_invert_size, do_neon_logic, do_neon_bitfield, neon_dyadic)
(do_neon_dyadic_if_su, do_neon_dyadic_if_su_d, do_neon_dyadic_if_i)
(do_neon_dyadic_if_i_d, do_neon_addsub_if_i, neon_exchange_operands)
(neon_compare, do_neon_cmp, do_neon_cmp_inv, do_neon_ceq)
(neon_scalar_for_mul, neon_mul_mac, do_neon_mac_maybe_scalar)
(do_neon_tst, do_neon_mul, do_neon_qdmulh, do_neon_fcmp_absolute)
(do_neon_fcmp_absolute_inv, do_neon_step, do_neon_abs_neg)
(do_neon_sli, do_neon_sri, do_neon_qshlu_imm, do_neon_qmovn)
(do_neon_qmovun, do_neon_rshift_sat_narrow)
(do_neon_rshift_sat_narrow_u, do_neon_movn, do_neon_rshift_narrow)
(do_neon_shll, neon_cvt_flavour, do_neon_cvt, neon_move_immediate)
(do_neon_mvn, neon_mixed_length, do_neon_dyadic_long, do_neon_abal)
(neon_mac_reg_scalar_long, do_neon_mac_maybe_scalar_long)
(do_neon_dyadic_wide, do_neon_vmull, do_neon_ext, do_neon_rev)
(do_neon_dup, do_neon_mov, do_neon_rshift_round_imm, do_neon_movl)
(do_neon_trn, do_neon_zip_uzp, do_neon_sat_abs_neg)
(do_neon_pair_long, do_neon_recip_est, do_neon_cls, do_neon_clz)
(do_neon_cnt, do_neon_swp, do_neon_tbl_tbx, do_neon_ldm_stm)
(do_neon_ldr_str, do_neon_ld_st_interleave, neon_alignment_bit)
(do_neon_ld_st_lane, do_neon_ld_dup, do_neon_ldx_stx): New
functions. Neon bit encoding and encoding helpers.
(parse_neon_type): New function. Parse Neon type specifier.
(opcode_lookup): Allow parsing of Neon type specifiers.
(REGNUM2, REGSETH, REGSET2): New macros.
(reg_names): Add new VFPv3 and Neon registers.
(NUF, nUF, NCE, nCE): New macros for opcode table.
(insns): More VFP registers allowed in fcpyd, fmdhr, fmdlr, fmrdh,
fmrdl, fabsd, fnegd, fsqrtd, faddd, fsubd, fmuld, fdivd, fmacd,
fmscd, fnmuld, fnmacd, fnmscd, fcmpd, fcmpzd, fcmped, fcmpezd,
fmdrr, fmrrd. Add Neon instructions vaba, vhadd, vrhadd, vhsub,
vqadd, vqsub, vrshl, vqrshl, vshl, vqshl{u}, vand, vbic, vorr, vorn,
veor, vbsl, vbit, vbif, vabd, vmax, vmin, vcge, vcgt, vclt, vcle,
vceq, vpmax, vpmin, vmla, vmls, vpadd, vadd, vsub, vtst, vmul,
vqdmulh, vqrdmulh, vacge, vacgt, vaclt, vacle, vrecps, vrsqrts,
vabs, vneg, v{r}shr, v{r}sra, vsli, vsri, vqshrn, vq{r}shr{u}n,
v{r}shrn, vshll, vcvt, vmov, vmvn, vabal, vabdl, vaddl, vsubl,
vmlal, vmlsl, vaddw, vsubw, v{r}addhn, v{r}subhn, vqdmlal, vqdmlsl,
vqdmull, vmull, vext, vrev64, vrev32, vrev16, vdup, vmovl, v{q}movn,
vzip, vuzp, vqabs, vqneg, vpadal, vpaddl, vrecpe, vrsqrte, vcls,
vclz, vcnt, vswp, vtrn, vtbl, vtbx, vldm, vstm, vldr, vstr,
vld[1234], vst[1234], fconst[sd], f[us][lh]to[sd], fto[us][lh][sd].
(tc_arm_regname_to_dw2regnum): Update for arm_reg_parse args.
(arm_cpu_option_table): Add Neon and VFPv3 to Cortex-A8.
(arm_option_cpu_value): Add vfp3 and neon.
(aeabi_set_public_attributes): Support VFPv3 and NEON attributes.
Fix VFPv1 attribute.
* gas/testsuite/gas/arm/copro.s: Avoid ldcl which encodes as a bad Neon
instruction.
* gas/testsuite/gas/arm/copro.d: Update accordingly.
* gas/testsuite/gas/arm/neon-cond.s: New test. Conditional Neon opcodes
in ARM mode.
* gas/testsuite/gas/arm/neon-cond.d: Expected results of above.
* gas/testsuite/gas/arm/neon-cov.s: New test. Coverage of Neon
instructions.
* gas/testsuite/gas/arm/neon-cov.d: Expected results of above.
* gas/testsuite/gas/arm/neon-ldst-es.s: New test. Element and structure
loads and stores.
* gas/testsuite/gas/arm/neon-ldst-es.d: Expected results of above.
* gas/testsuite/gas/arm/neon-ldst-rm.s: New test. Single and multiple
register loads and stores.
* gas/testsuite/gas/arm/neon-ldst-rm.d: Expected results of above.
* gas/testsuite/gas/arm/neon-omit.s: New test. Omission of optional
operands.
* gas/testsuite/gas/arm/neon-omit.d: Expected results of above.
* gas/testsuite/gas/arm/vfp1.d: Expect Neon syntax for some VFP
instructions.
* gas/testsuite/gas/arm/vfp1_t2.d: Likewise.
* gas/testsuite/gas/arm/vfp1xD.d: Likewise.
* gas/testsuite/gas/arm/vfp1xD_t2.d: Likewise.
* gas/testsuite/gas/arm/vfp2.d: Likewise.
* gas/testsuite/gas/arm/vfp2_t2.d: Likewise.
* gas/testsuite/gas/arm/vfp3-32drs.s: New test. Extended D register
range for VFP instructions.
* gas/testsuite/gas/arm/vfp3-32drs.d: Expected results of above.
* gas/testsuite/gas/arm/vfp3-const-conv.s: New test. VFPv3
constant-load and conversion instructions.
* gas/testsuite/gas/arm/vfp3-const-conv.d: Expected results of above.
* include/opcode/arm.h (FPU_VFP_EXT_V3): Define constant.
(FPU_NEON_EXT_V1): Likewise.
(FPU_VFP_HARD): Update.
(FPU_VFP_V3): Define macro.
(FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
* opcodes/arm-dis.c (coprocessor_opcodes): Add %A, %B, %k,
convert %<code>[zy] into %[zy]<code>. Expand meaning of
%<bitfield>['`?].
Add unified load/store instruction names.
(neon_opcode_table): New.
(arm_opcodes): Expand meaning of %<bitfield>['`?].
(arm_decode_bitfield): New.
(print_insn_coprocessor): Add pc argument. Add %A & %B specifiers.
Use arm_decode_bitfield and adjust numeric specifiers.
Adjust %z & %y.
(print_insn_neon): New.
(print_insn_arm): Adjust print_insn_coprocessor call. Call
print_insn_neon. Use arm_decode_bitfield and adjust numeric specifiers.
(print_insn_thumb32): Likewise.
195 lines
9.2 KiB
C
195 lines
9.2 KiB
C
/* ARM assembler/disassembler support.
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Copyright 2004 Free Software Foundation, Inc.
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This file is part of GDB and GAS.
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GDB and GAS are free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License as
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published by the Free Software Foundation; either version 1, or (at
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your option) any later version.
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GDB and GAS are distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GDB or GAS; see the file COPYING. If not, write to the
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Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
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02110-1301, USA. */
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/* The following bitmasks control CPU extensions: */
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#define ARM_EXT_V1 0x00000001 /* All processors (core set). */
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#define ARM_EXT_V2 0x00000002 /* Multiply instructions. */
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#define ARM_EXT_V2S 0x00000004 /* SWP instructions. */
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#define ARM_EXT_V3 0x00000008 /* MSR MRS. */
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#define ARM_EXT_V3M 0x00000010 /* Allow long multiplies. */
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#define ARM_EXT_V4 0x00000020 /* Allow half word loads. */
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#define ARM_EXT_V4T 0x00000040 /* Thumb. */
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#define ARM_EXT_V5 0x00000080 /* Allow CLZ, etc. */
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#define ARM_EXT_V5T 0x00000100 /* Improved interworking. */
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#define ARM_EXT_V5ExP 0x00000200 /* DSP core set. */
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#define ARM_EXT_V5E 0x00000400 /* DSP Double transfers. */
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#define ARM_EXT_V5J 0x00000800 /* Jazelle extension. */
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#define ARM_EXT_V6 0x00001000 /* ARM V6. */
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#define ARM_EXT_V6K 0x00002000 /* ARM V6K. */
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#define ARM_EXT_V6Z 0x00004000 /* ARM V6Z. */
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#define ARM_EXT_V6T2 0x00008000 /* Thumb-2. */
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#define ARM_EXT_DIV 0x00010000 /* Integer division. */
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/* The 'M' in Arm V7M stands for Microcontroller.
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On earlier architecture variants it stands for Multiply. */
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#define ARM_EXT_V5E_NOTM 0x00020000 /* Arm V5E but not Arm V7M. */
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#define ARM_EXT_V6_NOTM 0x00040000 /* Arm V6 but not Arm V7M. */
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#define ARM_EXT_V7 0x00080000 /* Arm V7. */
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#define ARM_EXT_V7A 0x00100000 /* Arm V7A. */
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#define ARM_EXT_V7R 0x00200000 /* Arm V7R. */
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#define ARM_EXT_V7M 0x00400000 /* Arm V7M. */
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/* Co-processor space extensions. */
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#define ARM_CEXT_XSCALE 0x00000001 /* Allow MIA etc. */
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#define ARM_CEXT_MAVERICK 0x00000002 /* Use Cirrus/DSP coprocessor. */
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#define ARM_CEXT_IWMMXT 0x00000004 /* Intel Wireless MMX technology coprocessor. */
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#define FPU_ENDIAN_PURE 0x80000000 /* Pure-endian doubles. */
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#define FPU_ENDIAN_BIG 0 /* Double words-big-endian. */
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#define FPU_FPA_EXT_V1 0x40000000 /* Base FPA instruction set. */
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#define FPU_FPA_EXT_V2 0x20000000 /* LFM/SFM. */
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#define FPU_MAVERICK 0x10000000 /* Cirrus Maverick. */
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#define FPU_VFP_EXT_V1xD 0x08000000 /* Base VFP instruction set. */
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#define FPU_VFP_EXT_V1 0x04000000 /* Double-precision insns. */
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#define FPU_VFP_EXT_V2 0x02000000 /* ARM10E VFPr1. */
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#define FPU_VFP_EXT_V3 0x01000000 /* VFPv3 insns. */
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#define FPU_NEON_EXT_V1 0x00800000 /* Neon (SIMD) insns. */
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/* Architectures are the sum of the base and extensions. The ARM ARM (rev E)
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defines the following: ARMv3, ARMv3M, ARMv4xM, ARMv4, ARMv4TxM, ARMv4T,
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ARMv5xM, ARMv5, ARMv5TxM, ARMv5T, ARMv5TExP, ARMv5TE. To these we add
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three more to cover cores prior to ARM6. Finally, there are cores which
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implement further extensions in the co-processor space. */
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#define ARM_AEXT_V1 ARM_EXT_V1
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#define ARM_AEXT_V2 (ARM_AEXT_V1 | ARM_EXT_V2)
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#define ARM_AEXT_V2S (ARM_AEXT_V2 | ARM_EXT_V2S)
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#define ARM_AEXT_V3 (ARM_AEXT_V2S | ARM_EXT_V3)
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#define ARM_AEXT_V3M (ARM_AEXT_V3 | ARM_EXT_V3M)
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#define ARM_AEXT_V4xM (ARM_AEXT_V3 | ARM_EXT_V4)
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#define ARM_AEXT_V4 (ARM_AEXT_V3M | ARM_EXT_V4)
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#define ARM_AEXT_V4TxM (ARM_AEXT_V4xM | ARM_EXT_V4T)
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#define ARM_AEXT_V4T (ARM_AEXT_V4 | ARM_EXT_V4T)
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#define ARM_AEXT_V5xM (ARM_AEXT_V4xM | ARM_EXT_V5)
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#define ARM_AEXT_V5 (ARM_AEXT_V4 | ARM_EXT_V5)
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#define ARM_AEXT_V5TxM (ARM_AEXT_V5xM | ARM_EXT_V4T | ARM_EXT_V5T)
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#define ARM_AEXT_V5T (ARM_AEXT_V5 | ARM_EXT_V4T | ARM_EXT_V5T)
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#define ARM_AEXT_V5TExP (ARM_AEXT_V5T | ARM_EXT_V5ExP)
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#define ARM_AEXT_V5TE (ARM_AEXT_V5TExP | ARM_EXT_V5E)
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#define ARM_AEXT_V5TEJ (ARM_AEXT_V5TE | ARM_EXT_V5J)
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#define ARM_AEXT_V6 (ARM_AEXT_V5TEJ | ARM_EXT_V6)
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#define ARM_AEXT_V6K (ARM_AEXT_V6 | ARM_EXT_V6K)
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#define ARM_AEXT_V6Z (ARM_AEXT_V6 | ARM_EXT_V6Z)
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#define ARM_AEXT_V6ZK (ARM_AEXT_V6 | ARM_EXT_V6K | ARM_EXT_V6Z)
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#define ARM_AEXT_V6T2 (ARM_AEXT_V6 | ARM_EXT_V6T2 | ARM_EXT_V6_NOTM)
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#define ARM_AEXT_V6KT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K)
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#define ARM_AEXT_V6ZT2 (ARM_AEXT_V6T2 | ARM_EXT_V6Z)
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#define ARM_AEXT_V6ZKT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K | ARM_EXT_V6Z)
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#define ARM_AEXT_V7_ARM (ARM_AEXT_V6ZKT2 | ARM_EXT_V7)
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#define ARM_AEXT_V7A (ARM_AEXT_V7_ARM | ARM_EXT_V7A)
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#define ARM_AEXT_V7R (ARM_AEXT_V7_ARM | ARM_EXT_V7R | ARM_EXT_DIV)
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#define ARM_AEXT_NOTM \
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(ARM_AEXT_V4 | ARM_EXT_V5ExP | ARM_EXT_V5J | ARM_EXT_V6_NOTM)
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#define ARM_AEXT_V7M \
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((ARM_AEXT_V7_ARM | ARM_EXT_V7M | ARM_EXT_DIV) & ~(ARM_AEXT_NOTM))
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#define ARM_AEXT_V7 (ARM_AEXT_V7A & ARM_AEXT_V7R & ARM_AEXT_V7M)
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/* Processors with specific extensions in the co-processor space. */
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#define ARM_ARCH_XSCALE ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE)
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#define ARM_ARCH_IWMMXT \
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ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE | ARM_CEXT_IWMMXT)
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#define FPU_VFP_V1xD (FPU_VFP_EXT_V1xD | FPU_ENDIAN_PURE)
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#define FPU_VFP_V1 (FPU_VFP_V1xD | FPU_VFP_EXT_V1)
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#define FPU_VFP_V2 (FPU_VFP_V1 | FPU_VFP_EXT_V2)
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#define FPU_VFP_V3 (FPU_VFP_V2 | FPU_VFP_EXT_V3)
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#define FPU_VFP_HARD (FPU_VFP_EXT_V1xD | FPU_VFP_EXT_V1 | FPU_VFP_EXT_V2 \
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| FPU_VFP_EXT_V3 | FPU_NEON_EXT_V1)
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#define FPU_FPA (FPU_FPA_EXT_V1 | FPU_FPA_EXT_V2)
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/* Deprecated */
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#define FPU_ARCH_VFP ARM_FEATURE (0, FPU_ENDIAN_PURE)
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#define FPU_ARCH_FPE ARM_FEATURE (0, FPU_FPA_EXT_V1)
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#define FPU_ARCH_FPA ARM_FEATURE (0, FPU_FPA)
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#define FPU_ARCH_VFP_V1xD ARM_FEATURE (0, FPU_VFP_V1xD)
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#define FPU_ARCH_VFP_V1 ARM_FEATURE (0, FPU_VFP_V1)
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#define FPU_ARCH_VFP_V2 ARM_FEATURE (0, FPU_VFP_V2)
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#define FPU_ARCH_VFP_V3 ARM_FEATURE (0, FPU_VFP_V3)
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#define FPU_ARCH_NEON_V1 ARM_FEATURE (0, FPU_NEON_EXT_V1)
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#define FPU_ARCH_VFP_V3_PLUS_NEON_V1 \
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ARM_FEATURE (0, FPU_VFP_V3 | FPU_NEON_EXT_V1)
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#define FPU_ARCH_VFP_HARD ARM_FEATURE (0, FPU_VFP_HARD)
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#define FPU_ARCH_ENDIAN_PURE ARM_FEATURE (0, FPU_ENDIAN_PURE)
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#define FPU_ARCH_MAVERICK ARM_FEATURE (0, FPU_MAVERICK)
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#define ARM_ARCH_V1 ARM_FEATURE (ARM_AEXT_V1, 0)
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#define ARM_ARCH_V2 ARM_FEATURE (ARM_AEXT_V2, 0)
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#define ARM_ARCH_V2S ARM_FEATURE (ARM_AEXT_V2S, 0)
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#define ARM_ARCH_V3 ARM_FEATURE (ARM_AEXT_V3, 0)
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#define ARM_ARCH_V3M ARM_FEATURE (ARM_AEXT_V3M, 0)
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#define ARM_ARCH_V4xM ARM_FEATURE (ARM_AEXT_V4xM, 0)
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#define ARM_ARCH_V4 ARM_FEATURE (ARM_AEXT_V4, 0)
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#define ARM_ARCH_V4TxM ARM_FEATURE (ARM_AEXT_V4TxM, 0)
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#define ARM_ARCH_V4T ARM_FEATURE (ARM_AEXT_V4T, 0)
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#define ARM_ARCH_V5xM ARM_FEATURE (ARM_AEXT_V5xM, 0)
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#define ARM_ARCH_V5 ARM_FEATURE (ARM_AEXT_V5, 0)
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#define ARM_ARCH_V5TxM ARM_FEATURE (ARM_AEXT_V5TxM, 0)
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#define ARM_ARCH_V5T ARM_FEATURE (ARM_AEXT_V5T, 0)
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#define ARM_ARCH_V5TExP ARM_FEATURE (ARM_AEXT_V5TExP, 0)
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#define ARM_ARCH_V5TE ARM_FEATURE (ARM_AEXT_V5TE, 0)
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#define ARM_ARCH_V5TEJ ARM_FEATURE (ARM_AEXT_V5TEJ, 0)
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#define ARM_ARCH_V6 ARM_FEATURE (ARM_AEXT_V6, 0)
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#define ARM_ARCH_V6K ARM_FEATURE (ARM_AEXT_V6K, 0)
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#define ARM_ARCH_V6Z ARM_FEATURE (ARM_AEXT_V6Z, 0)
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#define ARM_ARCH_V6ZK ARM_FEATURE (ARM_AEXT_V6ZK, 0)
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#define ARM_ARCH_V6T2 ARM_FEATURE (ARM_AEXT_V6T2, 0)
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#define ARM_ARCH_V6KT2 ARM_FEATURE (ARM_AEXT_V6KT2, 0)
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#define ARM_ARCH_V6ZT2 ARM_FEATURE (ARM_AEXT_V6ZT2, 0)
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#define ARM_ARCH_V6ZKT2 ARM_FEATURE (ARM_AEXT_V6ZKT2, 0)
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#define ARM_ARCH_V7 ARM_FEATURE (ARM_AEXT_V7, 0)
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#define ARM_ARCH_V7A ARM_FEATURE (ARM_AEXT_V7A, 0)
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#define ARM_ARCH_V7R ARM_FEATURE (ARM_AEXT_V7R, 0)
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#define ARM_ARCH_V7M ARM_FEATURE (ARM_AEXT_V7M, 0)
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/* Some useful combinations: */
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#define ARM_ARCH_NONE ARM_FEATURE (0, 0)
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#define FPU_NONE ARM_FEATURE (0, 0)
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#define ARM_ANY ARM_FEATURE (-1, 0) /* Any basic core. */
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#define FPU_ANY_HARD ARM_FEATURE (0, FPU_FPA | FPU_VFP_HARD | FPU_MAVERICK)
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#define ARM_ARCH_THUMB2 ARM_FEATURE (ARM_EXT_V6T2 | ARM_EXT_V7 | ARM_EXT_V7A | ARM_EXT_V7R | ARM_EXT_V7M | ARM_EXT_DIV, 0)
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/* There are too many feature bits to fit in a single word, so use a
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structure. For simplicity we put all core features in one word and
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everything else in the other. */
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typedef struct
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{
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unsigned long core;
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unsigned long coproc;
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} arm_feature_set;
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#define ARM_CPU_HAS_FEATURE(CPU,FEAT) \
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(((CPU).core & (FEAT).core) != 0 || ((CPU).coproc & (FEAT).coproc) != 0)
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#define ARM_MERGE_FEATURE_SETS(TARG,F1,F2) \
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do { \
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(TARG).core = (F1).core | (F2).core; \
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(TARG).coproc = (F1).coproc | (F2).coproc; \
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} while (0)
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#define ARM_CLEAR_FEATURE(TARG,F1,F2) \
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do { \
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(TARG).core = (F1).core &~ (F2).core; \
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(TARG).coproc = (F1).coproc &~ (F2).coproc; \
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} while (0)
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#define ARM_FEATURE(core, coproc) {(core), (coproc)}
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