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820dd5009b
Synopsys ARCv3 ISA includes 32-bit ARC HS5x targets and 64-bit ARC HS6x targets. Both CPU families are placed in "arc64" subdirectories as it done for GCC port. Target name arc64 is used for historical reasons and Synopsys ARCv3 baremetal toolchains contain multilib configurations both for 32-bit and 64-bit families. arc32 target name is reserved for 32-bit ARC HS5x targets in case of non-multilib 32-bit builds. Note that libgloss libraries for ARCv3 are compatible with libgloss for ARCv1/2. Thus, Makefile.inc for libgloss uses sources from libgloss/arc directory except crtX.S files. Co-authored-by: Shahab Vahedi <list@vahedi.org> Co-authored-by: Claudiu Zissulescu <claziss@gmail.com> Co-authored-by: Bruno Mauricio <brunoasmauricio@gmail.com> Co-authored-by: Luis Silva <luis.m.silva99@hotmail.com> Signed-off-by: Yuriy Kolerov <ykolerov@synopsys.com>
313 lines
7.5 KiB
ArmAsm
313 lines
7.5 KiB
ArmAsm
/*
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Copyright (c) 2024, Synopsys, Inc. All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1) Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2) Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3) Neither the name of the Synopsys, Inc., nor the names of its contributors
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may be used to endorse or promote products derived from this software
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without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/asm.h>
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; r0 void* dest
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; r1 const void* src
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; r2 size_t count
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; The 64-bit crunching implementation.
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#if defined (__ARC64_ARCH32__) && !defined(__ARC64_LL64__)
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ENTRY (memmove)
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; If the destination is greater than the source
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cmp r0, r1
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ADDP r4, r1, r2
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; or if the source plus count is smaller than the destination
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cmp.eq r4, r0
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; We can safely perform a normal memcpy. Otherwise, we need to perform it
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; backwards
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blo.d @.L_normal_memcpy
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lsr.f r11, r2, 4 ; counter for 16-byte chunks
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ADDP r3, r0, r2
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; Backwards search
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; The only thing that changes between memcpy and memmove is copy direction
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; in case the dest and src address memory locations overlap
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; More detailed information is in the forwards copy and at the end of
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; this document
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ADDP r1, r1, r2
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bmsk_s r2, r2, 3
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bbit0.d r2, 1, @1f
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lsr r5, r2, 2
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ldh.aw r4, [r1, -2]
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sth.aw r4, [r3, -2]
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1:
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bbit0.d r2, 0, @1f
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xor r5, r5, 3
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ldb.aw r4, [r1, -1]
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stb.aw r4, [r3, -1]
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1:
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asl r5, r5, 1
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bi [r5]
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ld.aw r4,[r1, -4]
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st.aw r4,[r3, -4]
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ld.aw r4,[r1, -4]
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st.aw r4,[r3, -4]
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ld.aw r4,[r1, -4]
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st.aw r4,[r3, -4]
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; Return if there are no 16 byte chunks
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jeq [blink]
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.L_write_backwards_16_bytes:
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ld.aw r4, [r1, -4]
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ld.aw r5, [r1, -4]
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ld.aw r6, [r1, -4]
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ld.aw r7, [r1, -4]
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st.aw r4, [r3, -4]
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st.aw r5, [r3, -4]
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st.aw r6, [r3, -4]
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dbnz.d r11, @.L_write_backwards_16_bytes
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st.aw r7, [r3, -4]
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j_s [blink]
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.L_normal_memcpy:
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beq.d @.L_write_forwards_15_bytes
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mov r3, r0 ; work on a copy of "r0"
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.L_write_forwards_16_bytes:
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ld.ab r4, [r1, 4]
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ld.ab r5, [r1, 4]
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ld.ab r6, [r1, 4]
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ld.ab r7, [r1, 4]
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st.ab r4, [r3, 4]
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st.ab r5, [r3, 4]
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st.ab r6, [r3, 4]
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dbnz.d r11, @.L_write_forwards_16_bytes
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st.ab r7, [r3, 4]
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bmsk_s r2, r2, 3
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.L_write_forwards_15_bytes:
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bbit0.d r2, 1, @1f
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lsr r11, r2, 2
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ldh.ab r4, [r1, 2]
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sth.ab r4, [r3, 2]
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1:
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bbit0.d r2, 0, @1f
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xor r11, r11, 3
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ldb.ab r4, [r1, 1]
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stb.ab r4, [r3, 1]
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1:
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asl r11, r11, 1
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bi [r11]
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ld.ab r4,[r1, 4]
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st.ab r4,[r3, 4]
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ld.ab r4,[r1, 4]
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st.ab r4,[r3, 4]
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ld r4,[r1]
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st r4,[r3]
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j_s [blink]
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ENDFUNC (memmove)
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#else
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ENTRY (memmove)
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; If the destination is greater than the source
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cmp r0, r1
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ADDP r4, r1, r2
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; or if the source plus count is smaller than the destination
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cmp.eq r4, r0
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; We can safely perform a normal memcpy. Otherwise, we need to perform it
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; backwards
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blo.d @.L_normal_memcpy
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LSRP.f r12, r2, 5 ; counter for 32-byte chunks
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ADDP r3, r0, r2
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; Backwards search
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; The only thing that changes between memcpy and memmove is copy direction
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; in case the dest and src address memory locations overlap
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; More detailed information is in the forwards copy and at the end of
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; this document
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; Set both r0 and r1 to point to the end of each memory location
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ADDP r1, r1, r2
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bmsk_s r2, r2, 4
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bbit0.d r2, 0, @1f
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lsr r11, r2, 3
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ldb.aw r4, [r1, -1]
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stb.aw r4, [r3, -1]
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1:
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bbit0.d r2, 1, @1f
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xor r11, r11, 3
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ldh.aw r4, [r1, -2]
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sth.aw r4, [r3, -2]
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1:
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bbit0.d r2, 2, @1f
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asl r11, r11, 1
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ld.aw r4, [r1, -4]
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st.aw r4, [r3, -4]
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1:
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bi [r11]
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LD64.aw r4, [r1, -8]
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ST64.aw r4, [r3, -8]
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LD64.aw r4, [r1, -8]
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ST64.aw r4, [r3, -8]
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LD64.aw r4, [r1, -8]
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ST64.aw r4, [r3, -8]
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; Jump if there are no 32 byte chunks
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jeq [blink]
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.L_write_backwards_32_bytes: ; Take care of 32 byte chunks
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#if defined (__ARC64_M128__)
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lddl.aw r4r5, [r1, -16]
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lddl.aw r6r7, [r1, -16]
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stdl.aw r4r5, [r3, -16]
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stdl.aw r6r7, [r3, -16]
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dbnz r12, @.L_write_backwards_32_bytes
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#elif defined (__ARC64_ARCH64__) || ( defined (__ARC64_ARCH32__) && defined (__ARC64_LL64__) )
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LD64.aw r4, [r1, -8]
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LD64.aw r6, [r1, -8]
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LD64.aw r8, [r1, -8]
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LD64.aw r10,[r1, -8]
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ST64.aw r4, [r3, -8]
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ST64.aw r6, [r3, -8]
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ST64.aw r8, [r3, -8]
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dbnz.d r12, @.L_write_backwards_32_bytes
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ST64.aw r10, [r3, -8]
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#else
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# error Unknown configuration
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#endif
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j_s [blink]
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; Normal memcpy
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.L_normal_memcpy:
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;LSRP.f r12, r2, 5 ; Moved up
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beq.d @.L_write_forwards_31_bytes
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MOVP r3, r0 ; do not clobber the "dest"
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.L_write_forwards_32_bytes: ; Take care of 32 byte chunks
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#if defined (__ARC64_M128__)
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lddl.ab r4r5, [r1, +16]
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lddl.ab r6r7, [r1, +16]
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stdl.ab r4r5, [r3, +16]
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stdl.ab r6r7, [r3, +16]
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dbnz r12, @.L_write_forwards_32_bytes
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#elif defined (__ARC64_ARCH64__) || ( defined (__ARC64_ARCH32__) && defined (__ARC64_LL64__) )
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LD64.ab r4, [r1, +8]
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LD64.ab r6, [r1, +8]
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LD64.ab r8, [r1, +8]
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LD64.ab r10,[r1, +8]
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ST64.ab r4, [r3, +8]
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ST64.ab r6, [r3, +8]
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ST64.ab r8, [r3, +8]
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dbnz.d r12, @.L_write_forwards_32_bytes
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ST64.ab r10, [r3, +8] ; Shove store in delay slot
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#else
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# error Unknown configuration
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#endif
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bmsk_s r2, r2, 4 ; From now on, we only care for the remainder % 32
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; The remainder bits indicating how many more bytes to copy
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; .------------------------.
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; | b4 | b3 | b2 | b1 | b0 |
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; `------------------------'
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; 16 8 4 2 1
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.L_write_forwards_31_bytes:
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bbit0.d r2, 2, @1f ; is b2 set? then copy 4 bytes
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lsr r12, r2, 3 ; see the notes below
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ld.ab r4, [r1, 4]
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st.ab r4, [r3, 4]
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1:
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bbit0.d r2, 1, @1f ; is b1 set? then copy 2 bytes
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xor r12, r12, 3
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ldh.ab r4, [r1, 2]
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sth.ab r4, [r3, 2]
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1:
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bbit0.d r2, 0, @1f ; is b0 set? then copy 1 byte
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asl r12, r12, 1
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ldb.ab r4, [r1, 1]
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stb.ab r4, [r3, 1]
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; Interpreting bits (b4,b3) [1] and how they correlate to branch index:
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;
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; (b4,b3) | bytes to copy | branch index
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; --------+---------------+-------------
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; 00b | 0 | 3 (11b)
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; 01b | 8 | 2 (10b)
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; 10b | 16 | 1 (01b)
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; 11b | 24 | 0 (00b)
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;
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; To go from (b4,b3) to branch index, the bits must be flipped.
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; In other words, they must be XORed with 11b [2].
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;
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; Last but not least, "bi" jumps at boundaries of 4. We need to double
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; the index to jump 8 bytes [3].
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;
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; Hence, the 3 operations for calculating the branch index that are spread
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; in "bbit0" delay slots:
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;
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; lsr r12, r2, 3 [1]
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; xor r12, r12, 3 [2]
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; asl r12, r12, 1 [3]
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1:
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bi [r12]
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LD64.ab r4, [r1, 8]
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ST64.ab r4, [r3, 8]
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LD64.ab r4, [r1, 8]
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ST64.ab r4, [r3, 8]
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LD64.ab r4, [r1, 8]
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ST64.ab r4, [r3, 8]
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j_s [blink]
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ENDFUNC (memmove)
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#endif
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