629 lines
14 KiB
ArmAsm
629 lines
14 KiB
ArmAsm
/*
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* interrupt_vectors.s -- the interrupt handler jump table.
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*
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*
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* There are a total of 32 interrupt vector possible, however, only
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* 11 of those are currently used (the others are reserved). The
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* order of vectors is as follows:
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*
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* 1. Boot Vector. Vector for power-on/reset.
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* 2. Software Vector. Vector for handling the SI instruction (an
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* explicit interrupt caused by software).
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* 3. Break Vector. Vector for handling the Break instruction.
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* 4. Device 0 Vector. Service vector for device zero.
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* 5. Device 1 Vector. Service vector for device one.
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* 6. Device 2 Vector. Service vector for device two.
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* 7. Device 3 Vector. Service vector for device three.
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* 8. Device 4 Vector. Service vector for device four.
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* 9. Device 5 Vector. Service vector for device five.
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* 10. Device 6 Vector. Service vector for device six.
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* 11. Device 7 Vector. Service vector for device seven.
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*
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* The rest of the interrupt vectors are reserved for future use.
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*
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*
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* Each jump table entry consists of the following two instructions:
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*
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* jmp Label ; Label as appropriate
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* nop ; implemented as or r0,r0,r0
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*
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* The following labels are reserved for the vectors named above,
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* respectively:
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*
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* _BOOTIVEC, _SOFTIVEC, _BRKIVEC, _DEV0IVEC, _DEV1IVEC, _DEV2IVEC,
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* _DEV3IVEC, _DEV4IVEC, _DEV5IVEC, _DEV6IVEC, _DEV7IVEC
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*
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*
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*
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* Copyright (c) 2001, 2002, 2003, 2004 Morpho Technologies
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*
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*/
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.section .startup, "a", @progbits
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.global __boot_start
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__boot_start:
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_INTERRUPT_VECTOR_TABLE:
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jmp _BOOTIVEC ; Boot vector
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or r0, r0, r0
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jmp _SOFTIVEC ; Vector for SI instruction
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or r0,r0,r0
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jmp _BRKIVEC ; Vector for Break instruction
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or r0,r0,r0
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; The illegal instruction trap is not implemented.
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_RESERVED1_IVEC:
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jmp _RESERVED1_IVEC ; Vector for illegal instruction
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or r0,r0,r0
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jmp _OVFIVEC ; Vector for overflow exception
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or r0,r0,r0
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_RESERVED2_IVEC:
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jmp _RESERVED2_IVEC
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or r0,r0,r0
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_RESERVED3_IVEC:
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jmp _RESERVED3_IVEC
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or r0,r0,r0
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_RESERVED4_IVEC:
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jmp _RESERVED4_IVEC
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or r0,r0,r0
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.text
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.equ SI_IOPORT_ADR, _DEBUG_SW_SYSREQ_REG
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.equ SI_IOPORT_BIT, 0x1
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.equ BRK_IOPORT_ADR, _DEBUG_BREAK_REG
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.equ BRK_IOPORT_BIT, 0x1
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.global _BOOTIVEC
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_BOOTIVEC:
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; Initialize the interrupt controller's interrupt vector registers
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ldui r1, #%hi16(_IVEC_DEFAULT)
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ori r1, r1, #%lo16(_IVEC_DEFAULT)
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stw r1, r0, #%lo16(_DEV0_INTERRUPT_REG)
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stw r1, r0, #%lo16(_DEV1_INTERRUPT_REG)
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stw r1, r0, #%lo16(_DEV2_INTERRUPT_REG)
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stw r1, r0, #%lo16(_DEV3_INTERRUPT_REG)
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stw r1, r0, #%lo16(_DEV4_INTERRUPT_REG)
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stw r1, r0, #%lo16(_DEV5_INTERRUPT_REG)
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stw r1, r0, #%lo16(_DEV6_INTERRUPT_REG)
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stw r1, r0, #%lo16(_DEV7_INTERRUPT_REG)
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stw r1, r0, #%lo16(_DEV8_INTERRUPT_REG)
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stw r1, r0, #%lo16(_DEV9_INTERRUPT_REG)
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stw r1, r0, #%lo16(_DEV10_INTERRUPT_REG)
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stw r1, r0, #%lo16(_DEV11_INTERRUPT_REG)
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stw r1, r0, #%lo16(_DEV12_INTERRUPT_REG)
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stw r1, r0, #%lo16(_DEV13_INTERRUPT_REG)
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stw r1, r0, #%lo16(_DEV14_INTERRUPT_REG)
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stw r1, r0, #%lo16(_DEV15_INTERRUPT_REG)
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stw r1, r0, #%lo16(_DEV16_INTERRUPT_REG)
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stw r1, r0, #%lo16(_DEV17_INTERRUPT_REG)
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stw r1, r0, #%lo16(_DEV18_INTERRUPT_REG)
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; Statically initialized data must be copied from ROM to RAM.
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; This is done in the C run-time start-up code (crt0.o).
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; Jump to the beginning of the application and enable interrupts.
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jmp _start
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ei
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; Handler for the SI instruction. To perform a system call, the
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; C model uses a trapping mechanism which executes an SI instruction.
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; The Morpho Technologies simulator simply performs a branch to
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; this vector to simulate the SI instruction (this is as the hardware
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; behaves). In order to trigger the simulator that a system call
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; is needed a write into the I/O register at address $40005 to
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; set bit #2 (0x4) is necessary.
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;
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; The above address has been changed to 0x00031C and the bit number
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; is zero. (The manifest constants have been changed to reflect this.)
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.global _SOFTIVEC
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_SOFTIVEC:
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; Build a frame to save registers.
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subi sp, sp, #$8
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stw r9, sp, #$4
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ldui r9, #%hi16(SI_IOPORT_ADR)
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stw r10, sp, #$0
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ori r9, r9, #%lo16(SI_IOPORT_ADR)
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ori r10, r0, #SI_IOPORT_BIT
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stw r10, r9, #$0
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or r0, r0, r0 ; SYS_call is handled by simulator here...
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ldw r10, sp, #$0
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or r0, r0, r0
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ldw r9, sp, #$4
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reti r14
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addi sp, sp, #$8
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; Handler for BREAK instruction. This handler triggers the simulator
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; to send a SIGTRAP signal to gdb by writing to the I/O register at
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; address $40005, setting bit #0 (0x1).
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;
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; The above address has been changed to 0x000304 and the bit number
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; is zero. (The manifest constants have been changed to reflect this.)
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.global _BRKIVEC
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_BRKIVEC:
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; Build a frame to save registers.
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subi sp, sp, #$8
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stw r9, sp, #$4
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ldui r9, #%hi16(BRK_IOPORT_ADR)
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stw r10, sp, #$0
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ori r9, r9, #%lo16(BRK_IOPORT_ADR)
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ori r10, r0, #BRK_IOPORT_BIT
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stw r10, r9, #$0
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or r0, r0, r0
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or r0, r0, r0
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or r0, r0, r0
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or r0, r0, r0
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or r0, r0, r0
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ldw r10, sp, #$0
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ldw r9, sp, #$4
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reti r15
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addi sp, sp, #$8
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; The documentation is lacking in the specification of the Overflow
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; Exception generation. The address of the instruction causing the
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; overflow is placed into R15 and the overflow exception interrupt
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; is triggered. So, to continue execution, return to the address
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; of the next instruction (i.e., R15 + one instruction).
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_OVFIVEC:
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addi r15, r15, #$4
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or r0, r0, r0
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reti r15
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or r0, r0, r0
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.global _IVEC_DEFAULT
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_IVEC_DEFAULT:
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reti r15
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or r0, r0, r0
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.section .internal_io, "a", @progbits
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.fill 256 ; Fill the first page.
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; This is the memory-mapped I/O region.
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; Hardware Interrupt Registers
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;.org 0xfff100
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.global _DEV0_INTERRUPT_REG
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_DEV0_INTERRUPT_REG:
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.word 0x00000000
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.global _DEV1_INTERRUPT_REG
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_DEV1_INTERRUPT_REG:
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.word 0x00000000
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.global _DEV2_INTERRUPT_REG
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_DEV2_INTERRUPT_REG:
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.word 0x00000000
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.global _DEV3_INTERRUPT_REG
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_DEV3_INTERRUPT_REG:
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.word 0x00000000
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.global _DEV4_INTERRUPT_REG
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_DEV4_INTERRUPT_REG:
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.word 0x00000000
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.global _DEV5_INTERRUPT_REG
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_DEV5_INTERRUPT_REG:
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.word 0x00000000
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.global _DEV6_INTERRUPT_REG
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_DEV6_INTERRUPT_REG:
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.word 0x00000000
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.global _DEV7_INTERRUPT_REG
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_DEV7_INTERRUPT_REG:
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.word 0x00000000
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.global _DEV8_INTERRUPT_REG
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_DEV8_INTERRUPT_REG:
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.word 0x00000000
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.global _DEV9_INTERRUPT_REG
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_DEV9_INTERRUPT_REG:
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.word 0x00000000
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.global _DEV10_INTERRUPT_REG
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_DEV10_INTERRUPT_REG:
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.word 0x00000000
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.global _DEV11_INTERRUPT_REG
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_DEV11_INTERRUPT_REG:
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.word 0x00000000
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.global _DEV12_INTERRUPT_REG
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_DEV12_INTERRUPT_REG:
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.word 0x00000000
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.global _DEV13_INTERRUPT_REG
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_DEV13_INTERRUPT_REG:
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.word 0x00000000
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.global _DEV14_INTERRUPT_REG
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_DEV14_INTERRUPT_REG:
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.word 0x00000000
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.global _DEV15_INTERRUPT_REG
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_DEV15_INTERRUPT_REG:
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.word 0x00000000
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.global _DEV16_INTERRUPT_REG
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_DEV16_INTERRUPT_REG:
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.word 0x00000000
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.global _DEV17_INTERRUPT_REG
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_DEV17_INTERRUPT_REG:
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.word 0x00000000
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.global _DEV18_INTERRUPT_REG
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_DEV18_INTERRUPT_REG:
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.word 0x00000000
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; 128 bytes minus ten registers (four bytes per register)
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.fill (128 - 19 * 4)
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.global _INTERRUPT_MASK_REG
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_INTERRUPT_MASK_REG:
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.word 0x00000000
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; 128 bytes minus one register (four bytes per register)
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.fill (128 - 1 * 4)
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;.org 0xfff200
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; MorphoSys Decoder Registers
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.global _MS_DEC_CIRC_BUFF_SEL_REG
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_MS_DEC_CIRC_BUFF_SEL_REG:
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.word 0x00000000
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.global _MS_DEC_SKIP_FACTOR_REG
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_MS_DEC_SKIP_FACTOR_REG:
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.word 0x00000000
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.global _MS_DEC_CUSTOM_PERM_REG
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_MS_DEC_CUSTOM_PERM_REG:
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.word 0x00000000
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.global _MS_DEC_CTXT_BASE_REG
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_MS_DEC_CTXT_BASE_REG:
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.word 0x00000000
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.global _MS_DEC_LOOKUP_TBL_REG
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_MS_DEC_LOOKUP_TBL_REG:
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.word 0x00000000
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.global _MS_CIRC_BUFF0_END_REG
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_MS_CIRC_BUFF0_END_REG:
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.word (__FRAME_BUFFER_END)
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.global _MS_CIRC_BUFF0_SIZE_REG
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_MS_CIRC_BUFF0_SIZE_REG:
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.word __FRAME_BUFFER_SIZE
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.global _MS_DATA_BLK0_END_REG
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_MS_DATA_BLK0_END_REG:
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.word 0x00000000
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.global _MS_DATA_BLK0_SIZE_REG
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_MS_DATA_BLK0_SIZE_REG:
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.word 0x00000000
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.global _MS_CIRC_BUFF1_END_REG
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_MS_CIRC_BUFF1_END_REG:
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.word (__FRAME_BUFFER_END)
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.global _MS_CIRC_BUFF1_SIZE_REG
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_MS_CIRC_BUFF1_SIZE_REG:
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.word __FRAME_BUFFER_SIZE
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.global _MS_DATA_BLK1_END_REG
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_MS_DATA_BLK1_END_REG:
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.word 0x00000000
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.global _MS_DATA_BLK1_SIZE_REG
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_MS_DATA_BLK1_SIZE_REG:
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.word 0x00000000
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.global _MS_CIRC_BUFF2_END_REG
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_MS_CIRC_BUFF2_END_REG:
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.word (__FRAME_BUFFER_END)
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.global _MS_CIRC_BUFF2_SIZE_REG
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_MS_CIRC_BUFF2_SIZE_REG:
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.word __FRAME_BUFFER_SIZE
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.global _MS_DATA_BLK2_END_REG
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_MS_DATA_BLK2_END_REG:
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.word 0x00000000
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.global _MS_DATA_BLK2_SIZE_REG
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_MS_DATA_BLK2_SIZE_REG:
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.word 0x00000000
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.global _MS_CIRC_BUFF3_END_REG
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_MS_CIRC_BUFF3_END_REG:
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.word (__FRAME_BUFFER_END)
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.global _MS_CIRC_BUFF3_SIZE_REG
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_MS_CIRC_BUFF3_SIZE_REG:
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.word __FRAME_BUFFER_SIZE
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.global _MS_DATA_BLK3_END_REG
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_MS_DATA_BLK3_END_REG:
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.word 0x00000000
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.global _MS_DATA_BLK3_SIZE_REG
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_MS_DATA_BLK3_SIZE_REG:
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.word 0x00000000
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|
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.global _MS_CIRC_BUFF4_END_REG
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_MS_CIRC_BUFF4_END_REG:
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.word (__FRAME_BUFFER_END)
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.global _MS_CIRC_BUFF4_SIZE_REG
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_MS_CIRC_BUFF4_SIZE_REG:
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.word __FRAME_BUFFER_SIZE
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|
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.global _MS_DATA_BLK4_END_REG
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_MS_DATA_BLK4_END_REG:
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.word 0x00000000
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|
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.global _MS_DATA_BLK4_SIZE_REG
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_MS_DATA_BLK4_SIZE_REG:
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.word 0x00000000
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|
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.global _MS_CIRC_BUFF5_END_REG
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_MS_CIRC_BUFF5_END_REG:
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.word (__FRAME_BUFFER_END)
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|
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.global _MS_CIRC_BUFF5_SIZE_REG
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_MS_CIRC_BUFF5_SIZE_REG:
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.word __FRAME_BUFFER_SIZE
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|
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.global _MS_DATA_BLK5_END_REG
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_MS_DATA_BLK5_END_REG:
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.word 0x00000000
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|
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.global _MS_DATA_BLK5_SIZE_REG
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_MS_DATA_BLK5_SIZE_REG:
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.word 0x00000000
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|
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.global _MS_CIRC_BUFF6_END_REG
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_MS_CIRC_BUFF6_END_REG:
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.word (__FRAME_BUFFER_END)
|
|
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.global _MS_CIRC_BUFF6_SIZE_REG
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_MS_CIRC_BUFF6_SIZE_REG:
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.word __FRAME_BUFFER_SIZE
|
|
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|
.global _MS_DATA_BLK6_END_REG
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|
_MS_DATA_BLK6_END_REG:
|
|
.word 0x00000000
|
|
|
|
.global _MS_DATA_BLK6_SIZE_REG
|
|
_MS_DATA_BLK6_SIZE_REG:
|
|
.word 0x00000000
|
|
|
|
.global _MS_CIRC_BUFF7_END_REG
|
|
_MS_CIRC_BUFF7_END_REG:
|
|
.word (__FRAME_BUFFER_END)
|
|
|
|
.global _MS_CIRC_BUFF7_SIZE_REG
|
|
_MS_CIRC_BUFF7_SIZE_REG:
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.word __FRAME_BUFFER_SIZE
|
|
|
|
.global _MS_DATA_BLK7_END_REG
|
|
_MS_DATA_BLK7_END_REG:
|
|
.word 0x00000000
|
|
|
|
.global _MS_DATA_BLK7_SIZE_REG
|
|
_MS_DATA_BLK7_SIZE_REG:
|
|
.word 0x00000000
|
|
|
|
.global _MS_DEC_AUTO_INC0_REG
|
|
_MS_DEC_AUTO_INC0_REG:
|
|
.word 0x00000000
|
|
|
|
.global _MS_DEC_AUTO_INC1_REG
|
|
_MS_DEC_AUTO_INC1_REG:
|
|
.word 0x00000000
|
|
|
|
.global _MS_DEC_AUTO_INC2_REG
|
|
_MS_DEC_AUTO_INC2_REG:
|
|
.word 0x00000000
|
|
|
|
.global _MS_DEC_AUTO_INC3_REG
|
|
_MS_DEC_AUTO_INC3_REG:
|
|
.word 0x00000000
|
|
|
|
.global _MS_DEC_AUTO_INC4_REG
|
|
_MS_DEC_AUTO_INC4_REG:
|
|
.word 0x00000000
|
|
|
|
.global _MS_DEC_AUTO_INC5_REG
|
|
_MS_DEC_AUTO_INC5_REG:
|
|
.word 0x00000000
|
|
|
|
.global _MS_DEC_AUTO_INC6_REG
|
|
_MS_DEC_AUTO_INC6_REG:
|
|
.word 0x00000000
|
|
|
|
.global _MS_DEC_AUTO_INC7_REG
|
|
_MS_DEC_AUTO_INC7_REG:
|
|
.word 0x00000000
|
|
|
|
|
|
; 256 bytes minus forty-five registers (four bytes per register)
|
|
.fill (256 - 45 * 4)
|
|
|
|
|
|
|
|
;.org 0xfff300
|
|
; Debug Registers
|
|
.global _DEBUG_HALT_REG
|
|
_DEBUG_HALT_REG:
|
|
.word 0x00000000
|
|
|
|
.global _DEBUG_BREAK_REG
|
|
_DEBUG_BREAK_REG:
|
|
.word 0x00000000
|
|
|
|
; There are five reserved registers.
|
|
.fill (5 * 4)
|
|
|
|
.global _DEBUG_SW_SYSREQ_REG
|
|
_DEBUG_SW_SYSREQ_REG:
|
|
.word 0x00000000
|
|
|
|
; 256 bytes minus eight registers (four bytes per register)
|
|
.fill (256 - 8 * 4)
|
|
|
|
|
|
|
|
;.org 0xfff400
|
|
; Sequence Generator Registers
|
|
.global _SEQ_GEN_CTRL_REG
|
|
_SEQ_GEN_CTRL_REG:
|
|
.word 0x00000000
|
|
|
|
.global _SEQ_GEN_MASK_REGS
|
|
_SEQ_GEN_MASK_REGS:
|
|
; The mask registers consume two pages (less one control register).
|
|
; 512 bytes minus one register (four bytes per register).
|
|
.fill (256 + 256 - 1 * 4)
|
|
|
|
|
|
|
|
;.org 0xfff600
|
|
; Timer Registers
|
|
.global _TIMER0_VAL_REG
|
|
_TIMER0_VAL_REG:
|
|
.word 0x00000000
|
|
|
|
.global _TIMER1_VAL_REG
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_TIMER1_VAL_REG:
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.word 0x00000000
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.global _TIMER2_VAL_REG
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_TIMER2_VAL_REG:
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.word 0x00000000
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.global _TIMER3_VAL_REG
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_TIMER3_VAL_REG:
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.word 0x00000000
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; 256 bytes minus four registers (four bytes per register)
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.fill (256 - 4 * 4)
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;.org 0xfff700
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; Output Line Control Registers
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.global _OUTPUT0_CTRL
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_OUTPUT0_CTRL:
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.word 0x00000000
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.global _OUTPUT1_CTRL
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_OUTPUT1_CTRL:
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.word 0x00000000
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.global _OUTPUT2_CTRL
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_OUTPUT2_CTRL:
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.word 0x00000000
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.global _OUTPUT3_CTRL
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_OUTPUT3_CTRL:
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.word 0x00000000
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.global _OUTPUT4_CTRL
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_OUTPUT4_CTRL:
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.word 0x00000000
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.global _OUTPUT5_CTRL
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_OUTPUT5_CTRL:
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.word 0x00000000
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.global _OUTPUT6_CTRL
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_OUTPUT6_CTRL:
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.word 0x00000000
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.global _OUTPUT7_CTRL
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_OUTPUT7_CTRL:
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.word 0x00000000
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.global _OUTPUT8_CTRL
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_OUTPUT8_CTRL:
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.word 0x00000000
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.global _OUTPUT9_CTRL
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_OUTPUT9_CTRL:
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.word 0x00000000
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.global _OUTPUT10_CTRL
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_OUTPUT10_CTRL:
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.word 0x00000000
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;; 128 bytes minus eleven registers (four bytes per register)
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;.fill (128 - 11 * 4)
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.global _INPUT0_CTRL
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_INPUT0_CTRL:
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.word 0x00000000
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;; 128 bytes minus one register (four bytes per register)
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;.fill (128 - 1 * 4)
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; 256 bytes minus twelve registers (four bytes per register)
|
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.fill (256 - 12 * 4)
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;.org 0xfff800
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; IQ Buffer Registers
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.global _IQ_BUFF_CTRL_REG
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_IQ_BUFF_CTRL_REG:
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.word 0x00000000
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.global _IQ_BUFF_PARAMETER1_REG
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_IQ_BUFF_PARAMETER1_REG:
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.word 0x00000000
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.global _IQ_BUFF_DATA_SIZE1_REG
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_IQ_BUFF_DATA_SIZE1_REG:
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.word 0x00000000
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.global _IQ_BUFF_TRANSFER_SIZE1_REG
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_IQ_BUFF_TRANSFER_SIZE1_REG:
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.word 0x00000000
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.global _IQ_BUFF_FB_ADDR1_REG
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_IQ_BUFF_FB_ADDR1_REG:
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.word 0x00000000
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.global _IQ_BUFF_PARAMETER2_REG
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_IQ_BUFF_PARAMETER2_REG:
|
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.word 0x00000000
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.global _IQ_BUFF_DATA_SIZE2_REG
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_IQ_BUFF_DATA_SIZE2_REG:
|
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.word 0x00000000
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.global _IQ_BUFF_TRANSFER_SIZE2_REG
|
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_IQ_BUFF_TRANSFER_SIZE2_REG:
|
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.word 0x00000000
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.global _IQ_BUFF_FB_ADDR2_REG
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_IQ_BUFF_FB_ADDR2_REG:
|
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.word 0x00000000
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|
|
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; 256 bytes minus nine registers (four bytes per register)
|
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.fill (256 - 9 * 4)
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|
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;.org 0xfff900
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; Reserved memory-mapped space.
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.fill (0x1000 - 0x900)
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