171 lines
4.1 KiB
ArmAsm
171 lines
4.1 KiB
ArmAsm
/*
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* Copyright (c) 2011 Aeroflex Gaisler
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*
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* BSD license:
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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/* The traptable has to be the first code in a boot PROM. */
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#include <asm-leon/head.h>
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#define TRAP(H) mov %psr, %l0; sethi %hi(H), %l4; jmp %l4+%lo(H); nop;
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#define TRAPL(H) nop; sethi %hi(H), %g1; jmp %g1+%lo(H); nop;
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#define TRAP_ENTRY(H) rd %psr, %l0; b H; rd %wim, %l3; nop;
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#define WIM_INIT 2
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#ifdef _SOFT_FLOAT
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#define PSR_INIT 0x0e0
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#else
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#define PSR_INIT 0x10e0
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#endif
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#define NUMREGWINDOWS 8
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/* Unexcpected trap will halt the processor by forcing it to error state */
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#define BAD_TRAP ta 0; nop; nop; nop;
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/* Software trap. Treat as BAD_TRAP */
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#define SOFT_TRAP BAD_TRAP
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.seg "text"
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.global _trap_table, start, _start, cpuinit, leonbare_irq_entry, _hardreset
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.global _window_overflow, _window_underflow, _flush_windows, _fpdis_enable
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/*.global _nwindows, _leon_version, _nwindows_min1*/
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!
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! Startup code for standalone system. Wash IU and FPU (if present) registers.
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! The registers have to be written to initiate the parity bits.
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!
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.section .text
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/* ------- */
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.weak _hardreset
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.set _hardreset,_hardreset_libgloss
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/* ------- */
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.global _hardreset_custom_weak, _hardreset_real, _cleanregs_custom_weak, _hardreset_custom_svt_weak
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_hardreset_real:
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nop
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_hardreset_libgloss:
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set _hardreset_custom_weak, %g1 ! possible mkprom init code here, default links to dummy _hardreset_custom_dummy
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call %g1
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nop
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set _trap_table, %g1 ! Initialize TBR
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mov %g1, %tbr
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set _hardreset_custom_svt_weak, %g1 ! give mkprom svt chance to reset tbr
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call %g1
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nop
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set _cleanregs_custom_weak, %g1
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call %g1
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nop
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#ifdef _FLAT
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mov %g0, %wim
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#else
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/* ! assume that %sp is correct use cwp of psr to set the next window as invalid
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mov %psr, %g2 ! extract cwp
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and 0x1f, %g2,%g2
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set 0x1, %g3
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sll %g3,%g2,%g3 ! the bit mask for cwp
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sll %g3, 1, %g4 ! rotate one to left
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sethi %hi(_nwindows_min1), %g5 ! NWINDOWS-1
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ld [%g5+%lo(_nwindows_min1)], %g5
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srl %g3, %g5, %g5
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or %g5, %g4, %g5
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mov %g5, %wim
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nop; nop; nop */
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#endif
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/*
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mov %psr, %g2
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set 0x202, %g3
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sll %g3, %g2, %g2
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mov %g2, %wim
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nop; nop; nop
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1:
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*/
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! -------------------------------
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! only cpu 0 initializes
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/* mov %psr, %g5
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srl %g5, 24, %g5
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and %g5, 3, %g5
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subcc %g5, 3, %g0 ! leon2: 0 or 2, leon3: 3
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bne callcpuinit
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nop
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*/
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rd %asr17,%g5
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srl %g5,28,%g5
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cmp %g5,%g0
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bne slavego
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nop
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callcpuinit:
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call cpuinit
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nop
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call pnpinit
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nop
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slavego:
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! -------------------------------
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sub %sp, 0x40, %sp ! room for main to save args
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call _start
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nop
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mov 1, %g1
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ta 0 ! Halt if _main would return ...
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nop
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.global _fpdis,_fpdis_svt
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_fpdis_svt:
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_fpdis:
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set 0x1000, %l4
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andcc %l0, %l4, %l3
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bne,a 4f
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andn %l0, %l4, %l0
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ta 0
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4:
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mov %l0, %psr ! restore %psr
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nop; nop; nop
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jmp %l2 ! Jump to nPC
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rett %l2 + 4
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/*
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!''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
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.section .bss
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.global _nwindows, _leon_version, _nwindows_min1
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_nwindows:
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.word 8
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_nwindows_min1:
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.word 7
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_leon_version:
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.word 3
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*/
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