491 lines
27 KiB
C
491 lines
27 KiB
C
/*
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* The authors hereby grant permission to use, copy, modify, distribute,
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* and license this software and its documentation for any purpose, provided
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* that existing copyright notices are retained in all copies and that this
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* notice is included verbatim in any distributions. No written agreement,
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* license, or royalty fee is required for any of the authorized uses.
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* Modifications to this software may be copyrighted by their authors
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* and need not follow the licensing terms described here, provided that
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* the new terms are clearly indicated on the first page of each file where
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* they apply.
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*/
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/*
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** Copyright (C) 2009 Analog Devices, Inc.
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**
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************************************************************************************
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**
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** This include file contains a list of macro "defines" to enable the programmer
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** to use symbolic names for register-access and bit-manipulation.
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**
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**/
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#ifndef _DEF_BF514_H
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#define _DEF_BF514_H
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/* Include all Core registers and bit definitions */
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#include <def_LPBlackfin.h>
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/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF514 */
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/* Include defBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
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#include <defBF51x_base.h>
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#ifdef _MISRA_RULES
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#pragma diag(push)
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#pragma diag(suppress:misra_rule_19_4:"macros violate rule 19.4")
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#endif /* _MISRA_RULES */
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/* The following are the #defines needed by ADSP-BF514 that are not in the common header */
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/* RSI Registers */
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#define RSI_PWR_CONTROL 0xFFC03800 /* RSI Power Control Register */
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/* legacy register name (below) provided for backwards code compatibility */
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#define SDH_PWR_CTL RSI_PWR_CONTROL /* SDH Power Control */
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#define RSI_CLK_CONTROL 0xFFC03804 /* RSI Clock Control Register */
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/* legacy register name (below) provided for backwards code compatibility */
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#define SDH_CLK_CTL RSI_CLK_CONTROL /* SDH Clock Control */
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#define RSI_ARGUMENT 0xFFC03808 /* RSI Argument Register */
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/* legacy register name (below) provided for backwards code compatibility */
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#define SDH_ARGUMENT RSI_ARGUMENT /* SDH Argument */
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#define RSI_COMMAND 0xFFC0380C /* RSI Command Register */
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/* legacy register name (below) provided for backwards code compatibility */
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#define SDH_COMMAND RSI_COMMAND /* SDH Command */
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#define RSI_RESP_CMD 0xFFC03810 /* RSI Response Command Register */
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/* legacy register name (below) provided for backwards code compatibility */
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#define SDH_RESP_CMD RSI_RESP_CMD /* SDH Response Command */
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#define RSI_RESPONSE0 0xFFC03814 /* RSI Response Register */
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/* legacy register name (below) provided for backwards code compatibility */
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#define SDH_RESPONSE0 RSI_RESPONSE0 /* SDH Response0 */
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#define RSI_RESPONSE1 0xFFC03818 /* RSI Response Register */
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/* legacy register name (below) provided for backwards code compatibility */
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#define SDH_RESPONSE1 RSI_RESPONSE1 /* SDH Response1 */
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#define RSI_RESPONSE2 0xFFC0381C /* RSI Response Register */
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/* legacy register name (below) provided for backwards code compatibility */
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#define SDH_RESPONSE2 RSI_RESPONSE2 /* SDH Response2 */
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#define RSI_RESPONSE3 0xFFC03820 /* RSI Response Register */
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/* legacy register name (below) provided for backwards code compatibility */
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#define SDH_RESPONSE3 RSI_RESPONSE3 /* SDH Response3 */
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#define RSI_DATA_TIMER 0xFFC03824 /* RSI Data Timer Register */
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/* legacy register name (below) provided for backwards code compatibility */
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#define SDH_DATA_TIMER RSI_DATA_TIMER /* SDH Data Timer */
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#define RSI_DATA_LGTH 0xFFC03828 /* RSI Data Length Register */
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/* legacy register name (below) provided for backwards code compatibility */
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#define SDH_DATA_LGTH RSI_DATA_LGTH /* SDH Data Length */
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#define RSI_DATA_CONTROL 0xFFC0382C /* RSI Data Control Register */
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/* legacy register name (below) provided for backwards code compatibility */
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#define SDH_DATA_CTL RSI_DATA_CONTROL /* SDH Data Control */
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#define RSI_DATA_CNT 0xFFC03830 /* RSI Data Counter Register */
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/* legacy register name (below) provided for backwards code compatibility */
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#define SDH_DATA_CNT RSI_DATA_CNT /* SDH Data Counter */
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#define RSI_STATUS 0xFFC03834 /* RSI Status Register */
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/* legacy register name (below) provided for backwards code compatibility */
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#define SDH_STATUS RSI_STATUS /* SDH Status */
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#define RSI_STATUSCL 0xFFC03838 /* RSI Status Clear Register */
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/* legacy register name (below) provided for backwards code compatibility */
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#define SDH_STATUS_CLR RSI_STATUSCL /* SDH Status Clear */
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#define RSI_MASK0 0xFFC0383C /* RSI Interrupt 0 Mask Register */
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/* legacy register name (below) provided for backwards code compatibility */
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#define SDH_MASK0 RSI_MASK0 /* SDH Interrupt0 Mask */
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#define RSI_MASK1 0xFFC03840 /* RSI Interrupt 1 Mask Register */
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/* legacy register name (below) provided for backwards code compatibility */
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#define SDH_MASK1 RSI_MASK1 /* SDH Interrupt1 Mask */
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#define RSI_FIFO_CNT 0xFFC03848 /* RSI FIFO Counter Register */
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/* legacy register name (below) provided for backwards code compatibility */
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#define SDH_FIFO_CNT RSI_FIFO_CNT /* SDH FIFO Counter */
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#define RSI_CEATA_CONTROL 0xFFC0384C /* RSI CEATA Register */
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#define RSI_FIFO 0xFFC03880 /* RSI Data FIFO Register */
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/* legacy register name (below) provided for backwards code compatibility */
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#define SDH_FIFO RSI_FIFO /* SDH Data FIFO */
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#define RSI_ESTAT 0xFFC038C0 /* RSI Exception Status Register */
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/* legacy register name (below) provided for backwards code compatibility */
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#define SDH_E_STATUS RSI_ESTAT /* SDH Exception Status */
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#define RSI_EMASK 0xFFC038C4 /* RSI Exception Mask Register */
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/* legacy register name (below) provided for backwards code compatibility */
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#define SDH_E_MASK RSI_EMASK /* SDH Exception Mask */
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#define RSI_CONFIG 0xFFC038C8 /* RSI Configuration Register */
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/* legacy register name (below) provided for backwards code compatibility */
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#define SDH_CFG RSI_CONFIG /* SDH Configuration */
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#define RSI_RD_WAIT_EN 0xFFC038CC /* RSI Read Wait Enable Register */
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/* legacy register name (below) provided for backwards code compatibility */
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#define SDH_RD_WAIT_EN RSI_RD_WAIT_EN /* SDH Read Wait Enable */
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#define RSI_PID0 0xFFC038D0 /* RSI Peripheral ID Register 0 */
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/* legacy register name (below) provided for backwards code compatibility */
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#define SDH_PID0 RSI_PID0 /* SDH Peripheral Identification0 */
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#define RSI_PID1 0xFFC038D4 /* RSI Peripheral ID Register 1 */
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/* legacy register name (below) provided for backwards code compatibility */
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#define SDH_PID1 RSI_PID1 /* SDH Peripheral Identification1 */
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#define RSI_PID2 0xFFC038D8 /* RSI Peripheral ID Register 2 */
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/* legacy register name (below) provided for backwards code compatibility */
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#define SDH_PID2 RSI_PID2 /* SDH Peripheral Identification2 */
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#define RSI_PID3 0xFFC038DC /* RSI Peripheral ID Register 3 */
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/* legacy register name (below) provided for backwards code compatibility */
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#define SDH_PID3 RSI_PID3 /* SDH Peripheral Identification3 */
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/* RSI Registers */
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/* ********************************************************** */
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/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
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/* and MULTI BIT READ MACROS */
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/* ********************************************************** */
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/* Bit masks for RSI_PWR_CONTROL */
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#define PWR_ON 0x3 /* Power On */
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#define RSI_CMD_OD 0x40 /* Open Drain Output */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define SD_CMD_OD RSI_CMD_OD /* Open Drain Output */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nSD_CMD_OD 0x0
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/* legacy bit mask (below) provided for backwards code compatibility */
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#if 0
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#define TBD 0x3c /* TBD */
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#endif
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define ROD_CTL 0x80
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nROD_CTL 0x80
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/* Bit masks for RSI_CLK_CONTROL */
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#define CLKDIV 0xff /* MC_CLK Divisor */
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#define CLK_EN 0x100 /* MC_CLK Bus Clock Enable */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define CLK_E CLK_EN /* MC_CLK Bus Clock Enable */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nCLK_E 0x0
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#define PWR_SV_EN 0x200 /* Power Save Enable */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define PWR_SV_E PWR_SV_EN /* Power Save Enable */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nPWR_SV_E 0x0
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#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nCLKDIV_BYPASS 0x0
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#define BUS_MODE 0x1800 /* Bus width selection */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define WIDE_BUS 0x0800 /* Wide Bus Mode Enable */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nWIDE_BUS 0x0
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/* Bit masks for RSI_COMMAND */
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#define CMD_IDX 0x3f /* Command Index */
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#define CMD_RSP_EN 0x40 /* Response */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define CMD_RSP CMD_RSP_EN /* Response */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nCMD_RSP 0x0
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#define CMD_LRSP_EN 0x80 /* Long Response */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define CMD_L_RSP CMD_LRSP_EN /* Long Response */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nCMD_L_RSP 0x0
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#define CMD_INT_EN 0x100 /* Command Interrupt */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define CMD_INT_E CMD_INT_EN /* Command Interrupt */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nCMD_INT_E 0x0
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#define CMD_PEND_EN 0x200 /* Command Pending */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define CMD_PEND_E CMD_PEND_EN /* Command Pending */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nCMD_PEND_E 0x0
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#define CMD_EN 0x400 /* Command Enable */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define CMD_E CMD_EN /* Command Enable */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nCMD_E 0x0
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/* Bit masks for RSI_RESP_CMD */
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#define RESP_CMD 0x3f /* Response Command */
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/* Bit masks for RSI_DATA_LGTH */
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#define DATA_LENGTH 0xffff /* Data Length */
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/* Bit masks for RSI_DATA_CONTROL */
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#define DATA_EN 0x1 /* Data Transfer Enable */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define DTX_E DATA_EN /* Data Transfer Enable */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nDTX_E 0x0
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#define DATA_DIR 0x2 /* Data Transfer Direction */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define DTX_DIR DATA_DIR /* Data Transfer Direction */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nDTX_DIR 0x0
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#define DATA_MODE 0x4 /* Data Transfer Mode */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define DTX_MODE DATA_MODE /* Data Transfer Mode */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nDTX_MODE 0x0
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#define DATA_DMA_EN 0x8 /* Data Transfer DMA Enable */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nDTX_DMA_E 0x0
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#define DATA_BLK_LGTH 0xf0 /* Data Transfer Block Length */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
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#define CEATA_EN 0x100 /* CE-ATA operation mode enable */
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#define CEATA_CCS_EN 0x200 /* CE-ATA CCS mode enable */
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/* Bit masks for RSI_DATA_CNT */
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#define DATA_COUNT 0xffff /* Data Count */
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/* Bit masks for RSI_STATUS */
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#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nCMD_CRC_FAIL 0x0
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#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nDAT_CRC_FAIL 0x0
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#define CMD_TIMEOUT 0x4 /* CMD Time Out */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nCMD_TIMEOUT 0x0
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#define DAT_TIMEOUT 0x8 /* Data Time Out */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nDAT_TIMEOUT 0x0
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#define TX_UNDERRUN 0x10 /* Transmit Underrun */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nTX_UNDERRUN 0x0
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#define RX_OVERRUN 0x20 /* Receive Overrun */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nRX_OVERRUN 0x0
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#define CMD_RESP_END 0x40 /* CMD Response End */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nCMD_RESP_END 0x0
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#define CMD_SENT 0x80 /* CMD Sent */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nCMD_SENT 0x0
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#define DAT_END 0x100 /* Data End */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nDAT_END 0x0
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#define START_BIT_ERR 0x200 /* Start Bit Error */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nSTART_BIT_ERR 0x0
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#define DAT_BLK_END 0x400 /* Data Block End */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nDAT_BLK_END 0x0
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#define CMD_ACT 0x800 /* CMD Active */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nCMD_ACT 0x0
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#define TX_ACT 0x1000 /* Transmit Active */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nTX_ACT 0x0
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#define RX_ACT 0x2000 /* Receive Active */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nRX_ACT 0x0
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#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nTX_FIFO_STAT 0x0
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#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nRX_FIFO_STAT 0x0
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#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nTX_FIFO_FULL 0x0
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#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nRX_FIFO_FULL 0x0
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#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nTX_FIFO_ZERO 0x0
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#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nRX_DAT_ZERO 0x0
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#define TX_DAT_RDY 0x100000 /* Transmit Data Available */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nTX_DAT_RDY 0x0
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#define RX_FIFO_RDY 0x200000 /* Receive Data Available */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nRX_FIFO_RDY 0x0
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/* Bit masks for RSI_STATCL */
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#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nCMD_CRC_FAIL_STAT 0x0
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#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nDAT_CRC_FAIL_STAT 0x0
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#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nCMD_TIMEOUT_STAT 0x0
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#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nDAT_TIMEOUT_STAT 0x0
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#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nTX_UNDERRUN_STAT 0x0
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#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nRX_OVERRUN_STAT 0x0
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#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nCMD_RESP_END_STAT 0x0
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#define CMD_SENT_STAT 0x80 /* CMD Sent Status */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nCMD_SENT_STAT 0x0
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#define DAT_END_STAT 0x100 /* Data End Status */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nDAT_END_STAT 0x0
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#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nSTART_BIT_ERR_STAT 0x0
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#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nDAT_BLK_END_STAT 0x0
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/* Bit masks for RSI_MASKx */
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#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nCMD_CRC_FAIL_MASK 0x0
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#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nDAT_CRC_FAIL_MASK 0x0
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#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nCMD_TIMEOUT_MASK 0x0
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#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nDAT_TIMEOUT_MASK 0x0
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#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nTX_UNDERRUN_MASK 0x0
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#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nRX_OVERRUN_MASK 0x0
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#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nCMD_RESP_END_MASK 0x0
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#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nCMD_SENT_MASK 0x0
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#define DAT_END_MASK 0x100 /* Data End Mask */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nDAT_END_MASK 0x0
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#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nSTART_BIT_ERR_MASK 0x0
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#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nDAT_BLK_END_MASK 0x0
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#define CMD_ACT_MASK 0x800 /* CMD Active Mask */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nCMD_ACT_MASK 0x0
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#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nTX_ACT_MASK 0x0
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#define RX_ACT_MASK 0x2000 /* Receive Active Mask */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nRX_ACT_MASK 0x0
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#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nTX_FIFO_STAT_MASK 0x0
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#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nRX_FIFO_STAT_MASK 0x0
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#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nTX_FIFO_FULL_MASK 0x0
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#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nRX_FIFO_FULL_MASK 0x0
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#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nTX_FIFO_ZERO_MASK 0x0
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#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nRX_DAT_ZERO_MASK 0x0
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#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nTX_DAT_RDY_MASK 0x0
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#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nRX_FIFO_RDY_MASK 0x0
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/* Bit masks for RSI_FIFO_CNT */
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#define FIFO_COUNT 0x7fff /* FIFO Count */
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/* Bit masks for RSI_CEATA_CONTROL */
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#define CEATA_TX_CCSD 0x1 /* Send CE-ATA CCSD sequence */
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/* Bit masks for RSI_ESTAT */
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#define SDIO_INT_DET 0x2 /* SDIO Int Detected */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nSDIO_INT_DET 0x0
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#define SD_CARD_DET 0x10 /* SD Card Detect */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nSD_CARD_DET 0x0
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#define CEATA_INT_DET 0x20
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/* Bit masks for RSI_EMASK */
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#define SDIO_INT_DET_MASK 0x2 /* Mask SDIO Int Detected */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define SDIO_MSK SDIO_INT_DET_MASK /* Mask SDIO Int Detected */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nSDIO_MSK 0x0
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#define SD_CARD_DET_MASK 0x10 /* Mask Card Detect */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define SCD_MASK SD_CARD_DET_MASK /* Mask Card Detect */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nSCD_MSK 0x0
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#define CEATA_INT_DET_MASK 0x20
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/* Bit masks for RSI_CFG */
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/* Left in for backwards compatibility */
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#define RSI_CLK_EN 0x1
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define CLKS_EN RSI_CLK_EN /* Clocks Enable */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nCLKS_EN 0x0
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#define SDIO4_EN 0x4 /* SDIO 4-Bit Enable */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define SD4E SDIO4_EN /* SDIO 4-Bit Enable */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nSD4E 0x0
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#define MW_EN 0x8 /* Moving Window Enable */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define MWE MW_EN /* Moving Window Enable */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nMWE 0x0
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#define RSI_RST 0x10 /* SDMMC Reset */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define SD_RST RSI_RST /* SDMMC Reset */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nSD_RST 0x0
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#define PU_DAT 0x20 /* Pull-up SD_DAT */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define PUP_SDDAT PU_DAT /* Pull-up SD_DAT */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nPUP_SDDAT 0x0
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#define PU_DAT3 0x40 /* Pull-up SD_DAT3 */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define PUP_SDDAT3 PU_DAT3 /* Pull-up SD_DAT3 */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nPUP_SDDAT3 0x0
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#define PD_DAT3 0x80 /* Pull-down SD_DAT3 */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define PD_SDDAT3 PD_DAT3 /* Pull-down SD_DAT3 */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nPD_SDDAT3 0x0
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/* Bit masks for RSI_RD_WAIT_EN */
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#define SDIO_RWR 0x1 /* Read Wait Request */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define RWR SDIO_RWR /* Read Wait Request */
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/* legacy bit mask (below) provided for backwards code compatibility */
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#define nRWR 0x0
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/* Bit masks for RSI_PIDx */
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#define RSI_PID 0xff /* RSI Peripheral ID */
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#ifdef _MISRA_RULES
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#pragma diag(pop)
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#endif /* _MISRA_RULES */
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#endif /* _DEF_BF514_H */
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