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96ec8f868e
Update AArch64 assembly string routines from: https://github.com/ARM-software/optimized-routines commit 0cf84f26b6b8dcad8287fe30a4dcc1fdabd06560 Author: Sebastian Huber <sebastian.huber@embedded-brains.de> Date: Thu Jul 27 17:14:57 2023 +0200 string: Fix corrupt GNU_PROPERTY_TYPE (5) size For ELF32 the notes alignment is 4 and not 8. Add license and copyright information to COPYING.NEWLIB as entry (56).
161 lines
3.1 KiB
ArmAsm
161 lines
3.1 KiB
ArmAsm
/*
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* strcpy/stpcpy - copy a string returning pointer to start/end.
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*
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* Copyright (c) 2020-2023, Arm Limited.
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* SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception
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*/
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#if (defined (__OPTIMIZE_SIZE__) || defined (PREFER_SIZE_OVER_SPEED))
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/* See strchr-stub.c */
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#else
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/* Assumptions:
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*
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* ARMv8-a, AArch64, Advanced SIMD.
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* MTE compatible.
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*/
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#include "asmdefs.h"
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#define dstin x0
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#define srcin x1
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#define result x0
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#define src x2
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#define dst x3
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#define len x4
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#define synd x4
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#define tmp x5
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#define shift x5
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#define data1 x6
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#define dataw1 w6
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#define data2 x7
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#define dataw2 w7
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#define dataq q0
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#define vdata v0
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#define vhas_nul v1
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#define vend v2
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#define dend d2
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#define dataq2 q1
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#ifdef BUILD_STPCPY
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# define STRCPY stpcpy
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# define IFSTPCPY(X,...) X,__VA_ARGS__
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#else
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# define STRCPY strcpy
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# define IFSTPCPY(X,...)
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#endif
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/*
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Core algorithm:
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For each 16-byte chunk we calculate a 64-bit nibble mask value with four bits
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per byte. We take 4 bits of every comparison byte with shift right and narrow
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by 4 instruction. Since the bits in the nibble mask reflect the order in
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which things occur in the original string, counting leading zeros identifies
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exactly which byte matched. */
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ENTRY (STRCPY)
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PTR_ARG (0)
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PTR_ARG (1)
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bic src, srcin, 15
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ld1 {vdata.16b}, [src]
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cmeq vhas_nul.16b, vdata.16b, 0
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lsl shift, srcin, 2
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shrn vend.8b, vhas_nul.8h, 4
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fmov synd, dend
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lsr synd, synd, shift
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cbnz synd, L(tail)
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ldr dataq, [src, 16]!
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cmeq vhas_nul.16b, vdata.16b, 0
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shrn vend.8b, vhas_nul.8h, 4
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fmov synd, dend
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cbz synd, L(start_loop)
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#ifndef __AARCH64EB__
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rbit synd, synd
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#endif
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sub tmp, src, srcin
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clz len, synd
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add len, tmp, len, lsr 2
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tbz len, 4, L(less16)
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sub tmp, len, 15
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ldr dataq, [srcin]
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ldr dataq2, [srcin, tmp]
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str dataq, [dstin]
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str dataq2, [dstin, tmp]
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IFSTPCPY (add result, dstin, len)
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ret
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L(tail):
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rbit synd, synd
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clz len, synd
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lsr len, len, 2
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L(less16):
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tbz len, 3, L(less8)
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sub tmp, len, 7
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ldr data1, [srcin]
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ldr data2, [srcin, tmp]
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str data1, [dstin]
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str data2, [dstin, tmp]
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IFSTPCPY (add result, dstin, len)
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ret
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.p2align 4
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L(less8):
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subs tmp, len, 3
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b.lo L(less4)
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ldr dataw1, [srcin]
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ldr dataw2, [srcin, tmp]
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str dataw1, [dstin]
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str dataw2, [dstin, tmp]
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IFSTPCPY (add result, dstin, len)
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ret
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L(less4):
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cbz len, L(zerobyte)
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ldrh dataw1, [srcin]
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strh dataw1, [dstin]
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L(zerobyte):
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strb wzr, [dstin, len]
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IFSTPCPY (add result, dstin, len)
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ret
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.p2align 4
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L(start_loop):
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sub tmp, srcin, dstin
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ldr dataq2, [srcin]
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sub dst, src, tmp
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str dataq2, [dstin]
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L(loop):
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str dataq, [dst], 32
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ldr dataq, [src, 16]
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cmeq vhas_nul.16b, vdata.16b, 0
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umaxp vend.16b, vhas_nul.16b, vhas_nul.16b
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fmov synd, dend
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cbnz synd, L(loopend)
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str dataq, [dst, -16]
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ldr dataq, [src, 32]!
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cmeq vhas_nul.16b, vdata.16b, 0
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umaxp vend.16b, vhas_nul.16b, vhas_nul.16b
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fmov synd, dend
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cbz synd, L(loop)
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add dst, dst, 16
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L(loopend):
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shrn vend.8b, vhas_nul.8h, 4 /* 128->64 */
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fmov synd, dend
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sub dst, dst, 31
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#ifndef __AARCH64EB__
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rbit synd, synd
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#endif
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clz len, synd
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lsr len, len, 2
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add dst, dst, len
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ldr dataq, [dst, tmp]
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str dataq, [dst]
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IFSTPCPY (add result, dst, 15)
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ret
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END (STRCPY)
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#endif
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