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96ec8f868e
Update AArch64 assembly string routines from: https://github.com/ARM-software/optimized-routines commit 0cf84f26b6b8dcad8287fe30a4dcc1fdabd06560 Author: Sebastian Huber <sebastian.huber@embedded-brains.de> Date: Thu Jul 27 17:14:57 2023 +0200 string: Fix corrupt GNU_PROPERTY_TYPE (5) size For ELF32 the notes alignment is 4 and not 8. Add license and copyright information to COPYING.NEWLIB as entry (56).
106 lines
2.1 KiB
ArmAsm
106 lines
2.1 KiB
ArmAsm
/*
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* strnlen - calculate the length of a string with limit.
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*
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* Copyright (c) 2020-2022, Arm Limited.
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* SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception
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*/
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#if (defined (__OPTIMIZE_SIZE__) || defined (PREFER_SIZE_OVER_SPEED))
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/* See strlen-stub.c */
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#else
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/* Assumptions:
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*
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* ARMv8-a, AArch64, Advanced SIMD.
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* MTE compatible.
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*/
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#include "asmdefs.h"
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#define srcin x0
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#define cntin x1
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#define result x0
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#define src x2
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#define synd x3
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#define shift x4
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#define tmp x4
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#define cntrem x5
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#define qdata q0
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#define vdata v0
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#define vhas_chr v1
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#define vend v2
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#define dend d2
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/*
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Core algorithm:
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Process the string in 16-byte aligned chunks. Compute a 64-bit mask with
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four bits per byte using the shrn instruction. A count trailing zeros then
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identifies the first zero byte. */
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ENTRY (strnlen)
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PTR_ARG (0)
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SIZE_ARG (1)
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bic src, srcin, 15
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cbz cntin, L(nomatch)
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ld1 {vdata.16b}, [src]
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cmeq vhas_chr.16b, vdata.16b, 0
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lsl shift, srcin, 2
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shrn vend.8b, vhas_chr.8h, 4 /* 128->64 */
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fmov synd, dend
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lsr synd, synd, shift
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cbz synd, L(start_loop)
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L(finish):
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rbit synd, synd
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clz synd, synd
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lsr result, synd, 2
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cmp cntin, result
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csel result, cntin, result, ls
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ret
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L(nomatch):
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mov result, cntin
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ret
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L(start_loop):
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sub tmp, src, srcin
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add tmp, tmp, 17
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subs cntrem, cntin, tmp
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b.lo L(nomatch)
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/* Make sure that it won't overread by a 16-byte chunk */
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tbz cntrem, 4, L(loop32_2)
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sub src, src, 16
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.p2align 5
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L(loop32):
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ldr qdata, [src, 32]!
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cmeq vhas_chr.16b, vdata.16b, 0
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umaxp vend.16b, vhas_chr.16b, vhas_chr.16b /* 128->64 */
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fmov synd, dend
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cbnz synd, L(end)
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L(loop32_2):
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ldr qdata, [src, 16]
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subs cntrem, cntrem, 32
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cmeq vhas_chr.16b, vdata.16b, 0
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b.lo L(end_2)
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umaxp vend.16b, vhas_chr.16b, vhas_chr.16b /* 128->64 */
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fmov synd, dend
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cbz synd, L(loop32)
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L(end_2):
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add src, src, 16
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L(end):
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shrn vend.8b, vhas_chr.8h, 4 /* 128->64 */
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sub result, src, srcin
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fmov synd, dend
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#ifndef __AARCH64EB__
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rbit synd, synd
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#endif
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clz synd, synd
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add result, result, synd, lsr 2
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cmp cntin, result
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csel result, cntin, result, ls
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ret
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END (strnlen)
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#endif
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