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9bba9c2bdd
It seems there is a swapped logic in one of the subcases of setjmp.S for MIPS: when the FPU registers are 64-bit within a 32-bit aligned jmp_buf, the code realigns the pointers before doing 64-bit writes, but the branch logic is swapped: we must avoid the address adjustement when bit 2 is zero (that is, the address is already 8-byte aligned). This always triggers an address error when run, as tested on a MIPS VR4300 with O64 ABI.