234 lines
6.8 KiB
ArmAsm
234 lines
6.8 KiB
ArmAsm
/* caches-asm.S -- cache manipulation for OpenRISC 1000.
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*
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* Copyright (c) 2011, 2014 Authors
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*
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* Contributor Julius Baxter <juliusbaxter@gmail.com>
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* Contributor Stefan Wallentowitz <stefan.wallentowitz@tum.de>
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*
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* The authors hereby grant permission to use, copy, modify, distribute,
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* and license this software and its documentation for any purpose, provided
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* that existing copyright notices are retained in all copies and that this
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* notice is included verbatim in any distributions. No written agreement,
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* license, or royalty fee is required for any of the authorized uses.
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* Modifications to this software may be copyrighted by their authors
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* and need not follow the licensing terms described here, provided that
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* the new terms are clearly indicated on the first page of each file where
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* they apply.
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*/
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#include "include/or1k-asm.h"
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#include "include/or1k-sprs.h"
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/* -------------------------------------------------------------------------- */
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/*!Function used at reset to clear and enable all caches
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*/
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/* -------------------------------------------------------------------------- */
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.global _or1k_cache_init
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.type _or1k_cache_init,@function
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_or1k_cache_init:
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/* Instruction cache enable */
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/* Check if IC present and skip enabling otherwise */
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l.mfspr r3,r0,OR1K_SPR_SYS_UPR_ADDR
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l.andi r4,r3,OR1K_SPR_SYS_UPR_ICP_MASK
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l.sfeq r4,r0
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OR1K_DELAYED_NOP(OR1K_INST(l.bf .Lnoic))
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/* Disable IC */
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l.mfspr r6,r0,OR1K_SPR_SYS_SR_ADDR
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l.addi r5,r0,-1
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l.xori r5,r5,OR1K_SPR_SYS_SR_ICE_MASK
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l.and r5,r6,r5
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l.mtspr r0,r5,OR1K_SPR_SYS_SR_ADDR
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/* Establish cache block size
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If BS=0, 16;
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If BS=1, 32;
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r14 contain block size
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*/
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l.mfspr r3,r0,OR1K_SPR_SYS_ICCFGR_ADDR
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l.andi r4,r3,OR1K_SPR_SYS_ICCFGR_CBS_MASK
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l.srli r7,r4,7
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l.ori r8,r0,16
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l.sll r14,r8,r7
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/* Establish number of cache sets
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r13 contains number of cache sets
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r7 contains log(# of cache sets)
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*/
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l.andi r4,r3,OR1K_SPR_SYS_ICCFGR_NCS_MASK
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l.srli r7,r4,3
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l.ori r8,r0,1
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l.sll r13,r8,r7
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/* Invalidate IC */
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l.addi r6,r0,0
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l.sll r5,r14,r7
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.Linvi: l.mtspr r0,r6,OR1K_SPR_ICACHE_ICBIR_ADDR
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l.sfne r6,r5
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OR1K_DELAYED(
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OR1K_INST(l.add r6,r6,r14),
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OR1K_INST(l.bf .Linvi)
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)
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/* Enable IC */
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l.mfspr r6,r0,OR1K_SPR_SYS_SR_ADDR
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l.ori r6,r6,OR1K_SPR_SYS_SR_ICE_MASK
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l.mtspr r0,r6,OR1K_SPR_SYS_SR_ADDR
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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/* Data cache enable */
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/* Check if DC present and skip enabling otherwise */
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.Lnoic: l.mfspr r3,r0,OR1K_SPR_SYS_UPR_ADDR
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l.andi r4,r3,OR1K_SPR_SYS_UPR_DCP_MASK
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l.sfeq r4,r0
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OR1K_DELAYED_NOP(OR1K_INST(l.bf .Lnodc))
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/* Disable DC */
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l.mfspr r6,r0,OR1K_SPR_SYS_SR_ADDR
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l.addi r5,r0,-1
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l.xori r5,r5,OR1K_SPR_SYS_SR_DCE_MASK
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l.and r5,r6,r5
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l.mtspr r0,r5,OR1K_SPR_SYS_SR_ADDR
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/* Establish cache block size
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If BS=0, 16;
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If BS=1, 32;
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r14 contain block size */
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l.mfspr r3,r0,OR1K_SPR_SYS_DCCFGR_ADDR
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l.andi r4,r3,OR1K_SPR_SYS_DCCFGR_CBS_MASK
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l.srli r7,r4,7
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l.ori r8,r0,16
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l.sll r14,r8,r7
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/* Establish number of cache sets
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r13 contains number of cache sets
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r7 contains log(# of cache sets) */
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l.andi r4,r3,OR1K_SPR_SYS_ICCFGR_NCS_MASK
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l.srli r7,r4,3
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l.ori r8,r0,1
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l.sll r13,r8,r7
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/* Invalidate DC */
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l.addi r6,r0,0
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l.sll r5,r14,r7
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.Linvd: l.mtspr r0,r6,OR1K_SPR_DCACHE_DCBIR_ADDR
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l.sfne r6,r5
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OR1K_DELAYED(
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OR1K_INST(l.add r6,r6,r14),
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OR1K_INST(l.bf .Linvd)
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)
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/* Enable DC */
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l.mfspr r6,r0,OR1K_SPR_SYS_SR_ADDR
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l.ori r6,r6,OR1K_SPR_SYS_SR_DCE_MASK
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l.mtspr r0,r6,OR1K_SPR_SYS_SR_ADDR
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.Lnodc:
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/* Return */
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OR1K_DELAYED_NOP(OR1K_INST(l.jr r9))
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/* -------------------------------------------------------------------------- */
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/*!Function to enable instruction cache
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*/
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/* -------------------------------------------------------------------------- */
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.global or1k_icache_enable
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.type or1k_icache_enable,@function
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or1k_icache_enable:
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/* Enable IC */
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l.mfspr r13,r0,OR1K_SPR_SYS_SR_ADDR
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l.ori r13,r13,OR1K_SPR_SYS_SR_ICE_MASK
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l.mtspr r0,r13,OR1K_SPR_SYS_SR_ADDR
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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OR1K_DELAYED_NOP(OR1K_INST(l.jr r9))
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/* -------------------------------------------------------------------------- */
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/*!Function to disable instruction cache
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*/
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/* -------------------------------------------------------------------------- */
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.global or1k_icache_disable
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.type or1k_icache_disable,@function
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or1k_icache_disable:
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/* Disable IC */
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l.mfspr r13,r0,OR1K_SPR_SYS_SR_ADDR
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l.addi r12,r0,-1
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l.xori r12,r12,OR1K_SPR_SYS_SR_ICE_MASK
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l.and r12,r13,r12
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l.mtspr r0,r12,OR1K_SPR_SYS_SR_ADDR
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OR1K_DELAYED_NOP(OR1K_INST(l.jr r9))
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/* -------------------------------------------------------------------------- */
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/*!Function to flush address of instruction cache
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*/
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/* -------------------------------------------------------------------------- */
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.global or1k_icache_flush
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.type or1k_icache_flush,@function
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or1k_icache_flush:
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OR1K_DELAYED(
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OR1K_INST(l.mtspr r0,r3,OR1K_SPR_ICACHE_ICBIR_ADDR),
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/* Push r3 into IC invalidate reg */
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OR1K_INST(l.jr r9)
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)
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/* -------------------------------------------------------------------------- */
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/*!Function to enable data cache
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*/
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/* -------------------------------------------------------------------------- */
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.global or1k_dcache_enable
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.type or1k_dcache_enable,@function
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or1k_dcache_enable:
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/* Enable DC */
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l.mfspr r13,r0,OR1K_SPR_SYS_SR_ADDR
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l.ori r13,r13,OR1K_SPR_SYS_SR_DCE_MASK
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l.mtspr r0,r13,OR1K_SPR_SYS_SR_ADDR
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l.nop
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l.nop
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l.nop
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l.nop
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l.nop
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OR1K_DELAYED_NOP(OR1K_INST(l.jr r9))
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/* -------------------------------------------------------------------------- */
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/*!Function to disable data cache
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*/
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/* -------------------------------------------------------------------------- */
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.global or1k_dcache_disable
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.type or1k_dcache_disable,@function
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or1k_dcache_disable:
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/* Disable DC */
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l.mfspr r13,r0,OR1K_SPR_SYS_SR_ADDR
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l.addi r12,r0,-1
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l.xori r12,r12,OR1K_SPR_SYS_SR_DCE_MASK
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l.and r12,r13,r12
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l.mtspr r0,r12,OR1K_SPR_SYS_SR_ADDR
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OR1K_DELAYED_NOP(OR1K_INST(l.jr r9))
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/* -------------------------------------------------------------------------- */
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/*!Function to flush address of data cache
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*/
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/* -------------------------------------------------------------------------- */
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.global or1k_dcache_flush
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.type or1k_dcache_flush,@function
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or1k_dcache_flush:
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OR1K_DELAYED(
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OR1K_INST(l.mtspr r0,r3,OR1K_SPR_DCACHE_DCBIR_ADDR),
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/* Push r3 into DC invalidate reg */
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OR1K_INST(l.jr r9)
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)
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