620 lines
15 KiB
ArmAsm
620 lines
15 KiB
ArmAsm
/* Copyright (c) 2013, Linaro Limited
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions
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are met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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* Neither the name of Linaro Limited nor the names of its
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contributors may be used to endorse or promote products derived
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from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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This memcpy routine is optimised for Cortex-A15 cores and takes advantage
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of VFP or NEON when built with the appropriate flags.
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Assumptions:
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ARMv6 (ARMv7-a if using Neon)
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ARM state
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Unaligned accesses
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LDRD/STRD support unaligned word accesses
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If compiled with GCC, this file should be enclosed within following
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pre-processing check:
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if defined (__ARM_ARCH_7A__) && defined (__ARM_FEATURE_UNALIGNED)
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*/
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.syntax unified
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/* This implementation requires ARM state. */
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.arm
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#ifdef __ARM_NEON__
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.fpu neon
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.arch armv7-a
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# define FRAME_SIZE 4
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# define USE_VFP
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# define USE_NEON
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#elif !defined (__SOFTFP__)
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.arch armv6
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.fpu vfpv2
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# define FRAME_SIZE 32
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# define USE_VFP
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#else
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.arch armv6
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# define FRAME_SIZE 32
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#endif
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/* Old versions of GAS incorrectly implement the NEON align semantics. */
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#ifdef BROKEN_ASM_NEON_ALIGN
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#define ALIGN(addr, align) addr,:align
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#else
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#define ALIGN(addr, align) addr:align
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#endif
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#define PC_OFFSET 8 /* PC pipeline compensation. */
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#define INSN_SIZE 4
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/* Call parameters. */
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#define dstin r0
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#define src r1
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#define count r2
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/* Locals. */
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#define tmp1 r3
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#define dst ip
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#define tmp2 r10
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#ifndef USE_NEON
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/* For bulk copies using GP registers. */
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#define A_l r2 /* Call-clobbered. */
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#define A_h r3 /* Call-clobbered. */
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#define B_l r4
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#define B_h r5
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#define C_l r6
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#define C_h r7
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#define D_l r8
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#define D_h r9
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#endif
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/* Number of lines ahead to pre-fetch data. If you change this the code
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below will need adjustment to compensate. */
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#define prefetch_lines 5
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#ifdef USE_VFP
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.macro cpy_line_vfp vreg, base
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vstr \vreg, [dst, #\base]
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vldr \vreg, [src, #\base]
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vstr d0, [dst, #\base + 8]
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vldr d0, [src, #\base + 8]
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vstr d1, [dst, #\base + 16]
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vldr d1, [src, #\base + 16]
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vstr d2, [dst, #\base + 24]
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vldr d2, [src, #\base + 24]
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vstr \vreg, [dst, #\base + 32]
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vldr \vreg, [src, #\base + prefetch_lines * 64 - 32]
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vstr d0, [dst, #\base + 40]
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vldr d0, [src, #\base + 40]
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vstr d1, [dst, #\base + 48]
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vldr d1, [src, #\base + 48]
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vstr d2, [dst, #\base + 56]
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vldr d2, [src, #\base + 56]
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.endm
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.macro cpy_tail_vfp vreg, base
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vstr \vreg, [dst, #\base]
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vldr \vreg, [src, #\base]
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vstr d0, [dst, #\base + 8]
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vldr d0, [src, #\base + 8]
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vstr d1, [dst, #\base + 16]
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vldr d1, [src, #\base + 16]
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vstr d2, [dst, #\base + 24]
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vldr d2, [src, #\base + 24]
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vstr \vreg, [dst, #\base + 32]
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vstr d0, [dst, #\base + 40]
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vldr d0, [src, #\base + 40]
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vstr d1, [dst, #\base + 48]
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vldr d1, [src, #\base + 48]
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vstr d2, [dst, #\base + 56]
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vldr d2, [src, #\base + 56]
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.endm
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#endif
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.macro def_fn f p2align=0
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.text
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.p2align \p2align
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.global \f
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.type \f, %function
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\f:
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.endm
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def_fn memcpy p2align=6
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mov dst, dstin /* Preserve dstin, we need to return it. */
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cmp count, #64
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bge .Lcpy_not_short
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/* Deal with small copies quickly by dropping straight into the
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exit block. */
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.Ltail63unaligned:
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#ifdef USE_NEON
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and tmp1, count, #0x38
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rsb tmp1, tmp1, #(56 - PC_OFFSET + INSN_SIZE)
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add pc, pc, tmp1
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vld1.8 {d0}, [src]! /* 14 words to go. */
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vst1.8 {d0}, [dst]!
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vld1.8 {d0}, [src]! /* 12 words to go. */
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vst1.8 {d0}, [dst]!
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vld1.8 {d0}, [src]! /* 10 words to go. */
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vst1.8 {d0}, [dst]!
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vld1.8 {d0}, [src]! /* 8 words to go. */
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vst1.8 {d0}, [dst]!
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vld1.8 {d0}, [src]! /* 6 words to go. */
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vst1.8 {d0}, [dst]!
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vld1.8 {d0}, [src]! /* 4 words to go. */
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vst1.8 {d0}, [dst]!
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vld1.8 {d0}, [src]! /* 2 words to go. */
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vst1.8 {d0}, [dst]!
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tst count, #4
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ldrne tmp1, [src], #4
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strne tmp1, [dst], #4
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#else
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/* Copy up to 15 full words of data. May not be aligned. */
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/* Cannot use VFP for unaligned data. */
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and tmp1, count, #0x3c
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add dst, dst, tmp1
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add src, src, tmp1
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rsb tmp1, tmp1, #(60 - PC_OFFSET/2 + INSN_SIZE/2)
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/* Jump directly into the sequence below at the correct offset. */
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add pc, pc, tmp1, lsl #1
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ldr tmp1, [src, #-60] /* 15 words to go. */
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str tmp1, [dst, #-60]
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ldr tmp1, [src, #-56] /* 14 words to go. */
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str tmp1, [dst, #-56]
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ldr tmp1, [src, #-52]
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str tmp1, [dst, #-52]
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ldr tmp1, [src, #-48] /* 12 words to go. */
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str tmp1, [dst, #-48]
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ldr tmp1, [src, #-44]
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str tmp1, [dst, #-44]
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ldr tmp1, [src, #-40] /* 10 words to go. */
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str tmp1, [dst, #-40]
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ldr tmp1, [src, #-36]
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str tmp1, [dst, #-36]
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ldr tmp1, [src, #-32] /* 8 words to go. */
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str tmp1, [dst, #-32]
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ldr tmp1, [src, #-28]
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str tmp1, [dst, #-28]
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ldr tmp1, [src, #-24] /* 6 words to go. */
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str tmp1, [dst, #-24]
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ldr tmp1, [src, #-20]
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str tmp1, [dst, #-20]
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ldr tmp1, [src, #-16] /* 4 words to go. */
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str tmp1, [dst, #-16]
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ldr tmp1, [src, #-12]
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str tmp1, [dst, #-12]
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ldr tmp1, [src, #-8] /* 2 words to go. */
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str tmp1, [dst, #-8]
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ldr tmp1, [src, #-4]
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str tmp1, [dst, #-4]
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#endif
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lsls count, count, #31
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ldrhcs tmp1, [src], #2
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ldrbne src, [src] /* Src is dead, use as a scratch. */
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strhcs tmp1, [dst], #2
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strbne src, [dst]
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bx lr
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.Lcpy_not_short:
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/* At least 64 bytes to copy, but don't know the alignment yet. */
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str tmp2, [sp, #-FRAME_SIZE]!
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and tmp2, src, #7
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and tmp1, dst, #7
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cmp tmp1, tmp2
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bne .Lcpy_notaligned
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#ifdef USE_VFP
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/* Magic dust alert! Force VFP on Cortex-A9. Experiments show
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that the FP pipeline is much better at streaming loads and
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stores. This is outside the critical loop. */
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vmov.f32 s0, s0
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#endif
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/* SRC and DST have the same mutual 32-bit alignment, but we may
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still need to pre-copy some bytes to get to natural alignment.
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We bring DST into full 64-bit alignment. */
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lsls tmp2, dst, #29
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beq 1f
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rsbs tmp2, tmp2, #0
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sub count, count, tmp2, lsr #29
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ldrmi tmp1, [src], #4
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strmi tmp1, [dst], #4
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lsls tmp2, tmp2, #2
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ldrhcs tmp1, [src], #2
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ldrbne tmp2, [src], #1
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strhcs tmp1, [dst], #2
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strbne tmp2, [dst], #1
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1:
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subs tmp2, count, #64 /* Use tmp2 for count. */
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blt .Ltail63aligned
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cmp tmp2, #512
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bge .Lcpy_body_long
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.Lcpy_body_medium: /* Count in tmp2. */
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#ifdef USE_VFP
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1:
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vldr d0, [src, #0]
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subs tmp2, tmp2, #64
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vldr d1, [src, #8]
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vstr d0, [dst, #0]
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vldr d0, [src, #16]
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vstr d1, [dst, #8]
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vldr d1, [src, #24]
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vstr d0, [dst, #16]
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vldr d0, [src, #32]
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vstr d1, [dst, #24]
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vldr d1, [src, #40]
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vstr d0, [dst, #32]
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vldr d0, [src, #48]
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vstr d1, [dst, #40]
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vldr d1, [src, #56]
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vstr d0, [dst, #48]
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add src, src, #64
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vstr d1, [dst, #56]
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add dst, dst, #64
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bge 1b
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tst tmp2, #0x3f
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beq .Ldone
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.Ltail63aligned: /* Count in tmp2. */
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and tmp1, tmp2, #0x38
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add dst, dst, tmp1
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add src, src, tmp1
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rsb tmp1, tmp1, #(56 - PC_OFFSET + INSN_SIZE)
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add pc, pc, tmp1
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vldr d0, [src, #-56] /* 14 words to go. */
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vstr d0, [dst, #-56]
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vldr d0, [src, #-48] /* 12 words to go. */
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vstr d0, [dst, #-48]
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vldr d0, [src, #-40] /* 10 words to go. */
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vstr d0, [dst, #-40]
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vldr d0, [src, #-32] /* 8 words to go. */
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vstr d0, [dst, #-32]
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vldr d0, [src, #-24] /* 6 words to go. */
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vstr d0, [dst, #-24]
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vldr d0, [src, #-16] /* 4 words to go. */
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vstr d0, [dst, #-16]
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vldr d0, [src, #-8] /* 2 words to go. */
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vstr d0, [dst, #-8]
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#else
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sub src, src, #8
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sub dst, dst, #8
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1:
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ldrd A_l, A_h, [src, #8]
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strd A_l, A_h, [dst, #8]
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ldrd A_l, A_h, [src, #16]
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strd A_l, A_h, [dst, #16]
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ldrd A_l, A_h, [src, #24]
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strd A_l, A_h, [dst, #24]
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ldrd A_l, A_h, [src, #32]
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strd A_l, A_h, [dst, #32]
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ldrd A_l, A_h, [src, #40]
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strd A_l, A_h, [dst, #40]
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ldrd A_l, A_h, [src, #48]
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strd A_l, A_h, [dst, #48]
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ldrd A_l, A_h, [src, #56]
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strd A_l, A_h, [dst, #56]
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ldrd A_l, A_h, [src, #64]!
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strd A_l, A_h, [dst, #64]!
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subs tmp2, tmp2, #64
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bge 1b
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tst tmp2, #0x3f
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bne 1f
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ldr tmp2,[sp], #FRAME_SIZE
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bx lr
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1:
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add src, src, #8
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add dst, dst, #8
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.Ltail63aligned: /* Count in tmp2. */
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/* Copy up to 7 d-words of data. Similar to Ltail63unaligned, but
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we know that the src and dest are 32-bit aligned so we can use
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LDRD/STRD to improve efficiency. */
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/* TMP2 is now negative, but we don't care about that. The bottom
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six bits still tell us how many bytes are left to copy. */
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and tmp1, tmp2, #0x38
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add dst, dst, tmp1
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add src, src, tmp1
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rsb tmp1, tmp1, #(56 - PC_OFFSET + INSN_SIZE)
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add pc, pc, tmp1
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ldrd A_l, A_h, [src, #-56] /* 14 words to go. */
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strd A_l, A_h, [dst, #-56]
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ldrd A_l, A_h, [src, #-48] /* 12 words to go. */
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strd A_l, A_h, [dst, #-48]
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ldrd A_l, A_h, [src, #-40] /* 10 words to go. */
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strd A_l, A_h, [dst, #-40]
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ldrd A_l, A_h, [src, #-32] /* 8 words to go. */
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strd A_l, A_h, [dst, #-32]
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ldrd A_l, A_h, [src, #-24] /* 6 words to go. */
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strd A_l, A_h, [dst, #-24]
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ldrd A_l, A_h, [src, #-16] /* 4 words to go. */
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strd A_l, A_h, [dst, #-16]
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ldrd A_l, A_h, [src, #-8] /* 2 words to go. */
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strd A_l, A_h, [dst, #-8]
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#endif
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tst tmp2, #4
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ldrne tmp1, [src], #4
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strne tmp1, [dst], #4
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lsls tmp2, tmp2, #31 /* Count (tmp2) now dead. */
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ldrhcs tmp1, [src], #2
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ldrbne tmp2, [src]
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strhcs tmp1, [dst], #2
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strbne tmp2, [dst]
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.Ldone:
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ldr tmp2, [sp], #FRAME_SIZE
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bx lr
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.Lcpy_body_long: /* Count in tmp2. */
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/* Long copy. We know that there's at least (prefetch_lines * 64)
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bytes to go. */
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#ifdef USE_VFP
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/* Don't use PLD. Instead, read some data in advance of the current
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copy position into a register. This should act like a PLD
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operation but we won't have to repeat the transfer. */
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vldr d3, [src, #0]
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vldr d4, [src, #64]
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vldr d5, [src, #128]
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vldr d6, [src, #192]
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vldr d7, [src, #256]
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vldr d0, [src, #8]
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vldr d1, [src, #16]
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vldr d2, [src, #24]
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add src, src, #32
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subs tmp2, tmp2, #prefetch_lines * 64 * 2
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blt 2f
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1:
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cpy_line_vfp d3, 0
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cpy_line_vfp d4, 64
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cpy_line_vfp d5, 128
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add dst, dst, #3 * 64
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add src, src, #3 * 64
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cpy_line_vfp d6, 0
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cpy_line_vfp d7, 64
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add dst, dst, #2 * 64
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add src, src, #2 * 64
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subs tmp2, tmp2, #prefetch_lines * 64
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bge 1b
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2:
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cpy_tail_vfp d3, 0
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cpy_tail_vfp d4, 64
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cpy_tail_vfp d5, 128
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add src, src, #3 * 64
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add dst, dst, #3 * 64
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cpy_tail_vfp d6, 0
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vstr d7, [dst, #64]
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vldr d7, [src, #64]
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vstr d0, [dst, #64 + 8]
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vldr d0, [src, #64 + 8]
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vstr d1, [dst, #64 + 16]
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vldr d1, [src, #64 + 16]
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vstr d2, [dst, #64 + 24]
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vldr d2, [src, #64 + 24]
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vstr d7, [dst, #64 + 32]
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add src, src, #96
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vstr d0, [dst, #64 + 40]
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vstr d1, [dst, #64 + 48]
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vstr d2, [dst, #64 + 56]
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add dst, dst, #128
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add tmp2, tmp2, #prefetch_lines * 64
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b .Lcpy_body_medium
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#else
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/* Long copy. Use an SMS style loop to maximize the I/O
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bandwidth of the core. We don't have enough spare registers
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to synthesise prefetching, so use PLD operations. */
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/* Pre-bias src and dst. */
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sub src, src, #8
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sub dst, dst, #8
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pld [src, #8]
|
|
pld [src, #72]
|
|
subs tmp2, tmp2, #64
|
|
pld [src, #136]
|
|
ldrd A_l, A_h, [src, #8]
|
|
strd B_l, B_h, [sp, #8]
|
|
ldrd B_l, B_h, [src, #16]
|
|
strd C_l, C_h, [sp, #16]
|
|
ldrd C_l, C_h, [src, #24]
|
|
strd D_l, D_h, [sp, #24]
|
|
pld [src, #200]
|
|
ldrd D_l, D_h, [src, #32]!
|
|
b 1f
|
|
.p2align 6
|
|
2:
|
|
pld [src, #232]
|
|
strd A_l, A_h, [dst, #40]
|
|
ldrd A_l, A_h, [src, #40]
|
|
strd B_l, B_h, [dst, #48]
|
|
ldrd B_l, B_h, [src, #48]
|
|
strd C_l, C_h, [dst, #56]
|
|
ldrd C_l, C_h, [src, #56]
|
|
strd D_l, D_h, [dst, #64]!
|
|
ldrd D_l, D_h, [src, #64]!
|
|
subs tmp2, tmp2, #64
|
|
1:
|
|
strd A_l, A_h, [dst, #8]
|
|
ldrd A_l, A_h, [src, #8]
|
|
strd B_l, B_h, [dst, #16]
|
|
ldrd B_l, B_h, [src, #16]
|
|
strd C_l, C_h, [dst, #24]
|
|
ldrd C_l, C_h, [src, #24]
|
|
strd D_l, D_h, [dst, #32]
|
|
ldrd D_l, D_h, [src, #32]
|
|
bcs 2b
|
|
/* Save the remaining bytes and restore the callee-saved regs. */
|
|
strd A_l, A_h, [dst, #40]
|
|
add src, src, #40
|
|
strd B_l, B_h, [dst, #48]
|
|
ldrd B_l, B_h, [sp, #8]
|
|
strd C_l, C_h, [dst, #56]
|
|
ldrd C_l, C_h, [sp, #16]
|
|
strd D_l, D_h, [dst, #64]
|
|
ldrd D_l, D_h, [sp, #24]
|
|
add dst, dst, #72
|
|
tst tmp2, #0x3f
|
|
bne .Ltail63aligned
|
|
ldr tmp2, [sp], #FRAME_SIZE
|
|
bx lr
|
|
#endif
|
|
|
|
.Lcpy_notaligned:
|
|
pld [src]
|
|
pld [src, #64]
|
|
/* There's at least 64 bytes to copy, but there is no mutual
|
|
alignment. */
|
|
/* Bring DST to 64-bit alignment. */
|
|
lsls tmp2, dst, #29
|
|
pld [src, #(2 * 64)]
|
|
beq 1f
|
|
rsbs tmp2, tmp2, #0
|
|
sub count, count, tmp2, lsr #29
|
|
ldrmi tmp1, [src], #4
|
|
strmi tmp1, [dst], #4
|
|
lsls tmp2, tmp2, #2
|
|
ldrbne tmp1, [src], #1
|
|
ldrhcs tmp2, [src], #2
|
|
strbne tmp1, [dst], #1
|
|
strhcs tmp2, [dst], #2
|
|
1:
|
|
pld [src, #(3 * 64)]
|
|
subs count, count, #64
|
|
ldrmi tmp2, [sp], #FRAME_SIZE
|
|
bmi .Ltail63unaligned
|
|
pld [src, #(4 * 64)]
|
|
|
|
#ifdef USE_NEON
|
|
vld1.8 {d0-d3}, [src]!
|
|
vld1.8 {d4-d7}, [src]!
|
|
subs count, count, #64
|
|
bmi 2f
|
|
1:
|
|
pld [src, #(4 * 64)]
|
|
vst1.8 {d0-d3}, [ALIGN (dst, 64)]!
|
|
vld1.8 {d0-d3}, [src]!
|
|
vst1.8 {d4-d7}, [ALIGN (dst, 64)]!
|
|
vld1.8 {d4-d7}, [src]!
|
|
subs count, count, #64
|
|
bpl 1b
|
|
2:
|
|
vst1.8 {d0-d3}, [ALIGN (dst, 64)]!
|
|
vst1.8 {d4-d7}, [ALIGN (dst, 64)]!
|
|
ands count, count, #0x3f
|
|
#else
|
|
/* Use an SMS style loop to maximize the I/O bandwidth. */
|
|
sub src, src, #4
|
|
sub dst, dst, #8
|
|
subs tmp2, count, #64 /* Use tmp2 for count. */
|
|
ldr A_l, [src, #4]
|
|
ldr A_h, [src, #8]
|
|
strd B_l, B_h, [sp, #8]
|
|
ldr B_l, [src, #12]
|
|
ldr B_h, [src, #16]
|
|
strd C_l, C_h, [sp, #16]
|
|
ldr C_l, [src, #20]
|
|
ldr C_h, [src, #24]
|
|
strd D_l, D_h, [sp, #24]
|
|
ldr D_l, [src, #28]
|
|
ldr D_h, [src, #32]!
|
|
b 1f
|
|
.p2align 6
|
|
2:
|
|
pld [src, #(5 * 64) - (32 - 4)]
|
|
strd A_l, A_h, [dst, #40]
|
|
ldr A_l, [src, #36]
|
|
ldr A_h, [src, #40]
|
|
strd B_l, B_h, [dst, #48]
|
|
ldr B_l, [src, #44]
|
|
ldr B_h, [src, #48]
|
|
strd C_l, C_h, [dst, #56]
|
|
ldr C_l, [src, #52]
|
|
ldr C_h, [src, #56]
|
|
strd D_l, D_h, [dst, #64]!
|
|
ldr D_l, [src, #60]
|
|
ldr D_h, [src, #64]!
|
|
subs tmp2, tmp2, #64
|
|
1:
|
|
strd A_l, A_h, [dst, #8]
|
|
ldr A_l, [src, #4]
|
|
ldr A_h, [src, #8]
|
|
strd B_l, B_h, [dst, #16]
|
|
ldr B_l, [src, #12]
|
|
ldr B_h, [src, #16]
|
|
strd C_l, C_h, [dst, #24]
|
|
ldr C_l, [src, #20]
|
|
ldr C_h, [src, #24]
|
|
strd D_l, D_h, [dst, #32]
|
|
ldr D_l, [src, #28]
|
|
ldr D_h, [src, #32]
|
|
bcs 2b
|
|
|
|
/* Save the remaining bytes and restore the callee-saved regs. */
|
|
strd A_l, A_h, [dst, #40]
|
|
add src, src, #36
|
|
strd B_l, B_h, [dst, #48]
|
|
ldrd B_l, B_h, [sp, #8]
|
|
strd C_l, C_h, [dst, #56]
|
|
ldrd C_l, C_h, [sp, #16]
|
|
strd D_l, D_h, [dst, #64]
|
|
ldrd D_l, D_h, [sp, #24]
|
|
add dst, dst, #72
|
|
ands count, tmp2, #0x3f
|
|
#endif
|
|
ldr tmp2, [sp], #FRAME_SIZE
|
|
bne .Ltail63unaligned
|
|
bx lr
|
|
|
|
.size memcpy, . - memcpy
|