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458 lines
18 KiB
C
458 lines
18 KiB
C
; @(#)intrinsi.h 1.4 90/10/14 20:56:06, Copyright 1988, 1989, 1990 AMD
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; start of file intrinsi.h
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; Copyright 1990 Advanced Micro Devices, Inc.
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;
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; This software is the property of Advanced Micro Devices, Inc (AMD) which
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; specifically grants the user the right to modify, use and distribute this
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; software provided this notice is not removed or altered. All other rights
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; are reserved by AMD.
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;
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; AMD MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS
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; SOFTWARE. IN NO EVENT SHALL AMD BE LIABLE FOR INCIDENTAL OR CONSEQUENTIAL
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; DAMAGES IN CONNECTION WITH OR ARISING FROM THE FURNISHING, PERFORMANCE, OR
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; USE OF THIS SOFTWARE.
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;
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; So that all may benefit from your experience, please report any problems
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; or suggestions about this software to the 29K Technical Support Center at
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; 800-29-29-AMD (800-292-9263) in the USA, or 0800-89-1131 in the UK, or
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; 0031-11-1129 in Japan, toll free. The direct dial number is 512-462-4118.
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;
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; Advanced Micro Devices, Inc.
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; 29K Support Products
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; Mail Stop 573
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; 5900 E. Ben White Blvd.
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; Austin, TX 78741
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; 800-292-9263
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;
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;
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.title "QTC Intrinsics Header file"
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;
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; Floating point library package for AMD 29000 family
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;
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; Copyright 1988 Advanced Micro Devices, Inc.
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;
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; All rights reserved
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;
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; Developed for AMD by Quantitative Technology Corporation
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; 8700 SW Creekside Place Suite D
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; Beaverton OR 97005
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; (503) 626-3081
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;
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; Version information :
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;
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; Revision 1.6 89/06/29 16:08:51 jimh
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; Fixed two bugs regarding compatiblility with the fpsymbol file. The
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; definitions of ROUND_TO_PLUS/MINUS_INFINITY were reversed. Set_Rounding
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; _Mode was fixed to set the local copy (29000 resident) of rounding mode
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; in 29027 mode.
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;
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;
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; Revision 1.5 89/04/17 11:20:49 jim
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; replaced emfsr and emtsr macro calls with mfsr and mtsr instructions.
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;
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; Revision 1.4 89/02/24 15:18:04 jimh
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; Added the definitions of FP_ENV_MODE_1_DEFAULT, FP_ENV_MODE_2_DEFAULT,
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; FP_FLAGS_DEFAULT.
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; Added macro clear_Flags.
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; Changed the operation of set_Invalid_Op_flag, set_Reserved_Op_flag.
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;
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; Revision 1.3 89/02/01 18:30:12 jimh
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; Changed the way set_Rounding_Mode, extract_Rounding_Mode, set_Invalid_Op_flag
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; and set_Reserved_Op_flag are done. Changed save_FP_regs.
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;
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; Revision 1.2 89/01/31 10:01:54 jimh
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; Updated to the new standard. This includes moving in register
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; definitions, changing old symbols to reflect those in fpsymbol.h,
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; and changing the include file to smartmac.h.
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;
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;
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.include "../traps/fpenv.h" ; RPD 8/21/89
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.include "sys/smartmac.h"
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.equ DOUBLE_EXP_WIDTH, 11
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.equ DOUBLE_EXTENDED_WIDTH, 56
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.equ SIGNED, 0
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.equ UNSIGNED, 1
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.equ ROUND_TO_NEAREST, 0
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.equ ROUND_TO_MINUS_INFINITY, 1
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.equ ROUND_TO_PLUS_INFINITY, 2
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.equ ROUND_TO_ZERO, 3
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.equ ROUNDING_MODE_POSITION, 14
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.equ FORMAT_INTEGER, 0
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.equ FORMAT_SINGLE, 1
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.equ FORMAT_DOUBLE, 2
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.equ DOUBLE_MSB_MASK,0x00080000
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;
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; The following are definitions used in the smart macro package, defining
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; the 29000 shadow registers for the floating-point register file, and
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; some temporary registers used during the library routines
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;
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.reg FP0, gr96
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.reg FP1, gr98
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.reg FP2, gr100
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.reg FP3, gr102
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.reg FP4, gr104
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.reg FP5, gr106
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.reg FP6, gr108
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.reg FP7, gr110
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;
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; GR60 through GR6F are used to return the value of a function
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;
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.reg rtn0, gr96
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.reg rtn1, gr97
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.reg rtn2, gr98
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.reg rtn3, gr99
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.reg rtn4, gr100
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.reg rtn5, gr101
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.reg rtn6, gr102
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.reg rtn7, gr103
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.reg rtn8, gr104
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.reg rtn9, gr105
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.reg rtn10, gr106
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.reg rtn11, gr107
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.reg rtn12, gr108
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.reg rtn13, gr109
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.reg rtn14, gr110
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.reg rtn15, gr111
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;
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; GR74..GR78 (116-120) - temporaries
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;
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.reg t0, gr116
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.reg t1, gr117
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.reg t2, gr118
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.reg t3, gr119
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.reg t4, gr120
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;
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; FP_ENV_MODE_1 and FP_ENV_MODE_2 are based on 64-bit 29027 Mode register,
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; and thus the fpsymbol.h CP_ constants may be used directly.
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;
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; FP_ENV_MODE_1 (Bits 0-31)
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;
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; 0-3 - floating-point format select, always 0
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; 4 - Saturate enable
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; 5 - IEEE Affine/Projective mode (ignored by traps code)
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; 6 - IEEE Trap enable
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; 7 - IEEE Sudden underflow / FP Environment Fast Float Select
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; 8-10 - ignored
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; 11 - Integer multiplication signed/unsigned select
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; 12-13 - Integer multiplication format adjust
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; 14-16 - Rounding mode select
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; 17-19 - ignored
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; 20 - Pipeline mode select
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; 21 - ignored
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; 22 - Invalid operation mask bit
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; 23 - Reserved operand mask bit
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; 24 - Overflow mask bit
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; 25 - Underflow mask bit
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; 26 - Inexact result mask bit
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; 27 - Zero mask bit
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; 28-31 - ignored
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;
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; FP_ENV_MODE_2 (Bits 32-63) [Hardware configuration register, rarely modified]
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;
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; 32-35 - Pipeline timer count
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; 36-39 - Timer count for multiply-accumulate operation
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; 40-43 - Timer count for save state transaction request
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; 44-63 - ignored
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;
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; FP_ENV_MODE_1 definitions
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;
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.set FP_ENV_MODE_1_DEFAULT, CP_PFF_EQ_IEEE
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.set FP_ENV_MODE_1_DEFAULT,FP_ENV_MODE_1_DEFAULT|CP_AFF_EQ_IEEE
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.set FP_ENV_MODE_1_DEFAULT,FP_ENV_MODE_1_DEFAULT|CP_AFFINE_MODE
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.set FP_ENV_MODE_1_DEFAULT,FP_ENV_MODE_1_DEFAULT|CP_IEEE_TRAPS_DISABLED
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.set FP_ENV_MODE_1_DEFAULT,FP_ENV_MODE_1_DEFAULT|CP_IEEE_GRADUAL_UFLOW_MODE
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.set FP_ENV_MODE_1_DEFAULT,FP_ENV_MODE_1_DEFAULT|CP_UNSIGNED_INT_MPY_MODE
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.set FP_ENV_MODE_1_DEFAULT,FP_ENV_MODE_1_DEFAULT|CP_MF_EQ_LSBS
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.set FP_ENV_MODE_1_DEFAULT,FP_ENV_MODE_1_DEFAULT|CP_RMS_EQ_NEAREST
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.set FP_ENV_MODE_1_DEFAULT,FP_ENV_MODE_1_DEFAULT|CP_FLOWTHROUGH_MODE
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.set FP_ENV_MODE_1_DEFAULT,FP_ENV_MODE_1_DEFAULT|CP_INVALID_OP_EXCP_MASK
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.set FP_ENV_MODE_1_DEFAULT,FP_ENV_MODE_1_DEFAULT|CP_RESERVED_OP_EXCP_MASK
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.set FP_ENV_MODE_1_DEFAULT,FP_ENV_MODE_1_DEFAULT|CP_OVERFLOW_EXCP_MASK
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.set FP_ENV_MODE_1_DEFAULT,FP_ENV_MODE_1_DEFAULT|CP_UNDERFLOW_EXCP_MASK
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.set FP_ENV_MODE_1_DEFAULT,FP_ENV_MODE_1_DEFAULT|CP_INEXACT_EXCP_MASK
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.set FP_ENV_MODE_1_DEFAULT,FP_ENV_MODE_1_DEFAULT|CP_ZERO_EXCP_MASK
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;
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; FP_ENV_MODE_2 definitions
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;
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.set FP_ENV_MODE_2_DEFAULT, CP_PLTC_EQ_6
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.set FP_ENV_MODE_2_DEFAULT,FP_ENV_MODE_2_DEFAULT|CP_MATC_EQ_9
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.set FP_ENV_MODE_2_DEFAULT,FP_ENV_MODE_2_DEFAULT|CP_MVTC_EQ_3
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.set FP_ENV_MODE_2_DEFAULT,FP_ENV_MODE_2_DEFAULT|CP_NORMAL_DRDY_MODE
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.set FP_ENV_MODE_2_DEFAULT,FP_ENV_MODE_2_DEFAULT|CP_HALT_ON_ERROR_DISABLED
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.set FP_ENV_MODE_2_DEFAULT,FP_ENV_MODE_2_DEFAULT|CP_EXCP_DISABLED
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;
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; FP_FLAGS_DEFAULT definitions
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;
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.equ FP_FLAGS_DEFAULT, 0x00000000 ; No flags set
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;
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; The following macros are used by transcendentals to access the environment.
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;
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; MACRO NAME: clear_Flags
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;
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; FUNCTION: to clear the flags on entry to a transcendental routine.
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;
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; INPUT PARAMETERS: reg - temporary working register
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; reg2 - temporary working register
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;
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.macro clear_Flags,reg,reg2
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.endm
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;
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; MACRO NAME: set_Invalid_Op_flag
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;
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; FUNCTION: to set the Invalid operation flag in the floating-point status
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; register
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;
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; INPUT PARAMETERS: reg - temporary working register
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; reg2 - 2nd temporary working register
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;
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.macro set_Invalid_Op_flag,reg,reg2
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.endm
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;
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; MACRO NAME: set_Reserved_Op_flag
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;
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; FUNCTION: to set the Reserved Op flag in the floating-point status register
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;
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; INPUT PARAMETERS: reg - temporary working register
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; reg2 - 2nd temporary working register
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;
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.macro set_Reserved_Op_flag,reg,reg2
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.endm
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;
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; MACRO NAME: extract_Rounding_Mode
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;
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; FUNCTION: to extract the Rounding Mode portion of the floating-point
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; invironment mode register, shift the value to the range of
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; 0-7, and leave it in a register
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;
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; INPUT PARAMETERS: reg - destination for the mode
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;
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.macro extract_Rounding_Mode,reg
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.ifdef _29027_MODE
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.extern __29027Mode
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const reg,__29027Mode
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consth reg,__29027Mode
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load 0,0,reg,reg
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srl reg,reg,CP_RMS_POSITION
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and reg,reg,CP_RMS_MASK >> CP_RMS_POSITION
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.else
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mfsr reg,FPE
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and reg,reg,FPE_FPRND_MASK
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srl reg,reg,FPE_FPRND_POSITION
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.endif
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.endm
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;
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; MACRO NAME: set_Rounding_Mode
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;
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; FUNCTION: to set the 29027 Rounding Mode to a given value
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;
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; INPUT PARAMETERS: reg - working register
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; reg2 - second working register
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; rounding_mode - value of the rounding mode
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; 0 - round to nearest
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; 1 - round to minus infinity
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; 2 - round to plus infinity
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; 3 - round to zero
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;
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; NOTES: rounding_mode value is not checked
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; 29027 Mode register is NOT written by this macro
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;
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.macro set_Rounding_Mode,reg,reg2,mode
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.ifdef _29027_MODE
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.extern __29027Mode
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const reg2,__29027Mode
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consth reg2,__29027Mode
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load 0,0,reg,reg2
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const reg2,CP_RMS_MASK
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consth reg2,CP_RMS_MASK
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andn reg,reg,reg2
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const reg2,mode
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sll reg2,reg2,CP_RMS_POSITION
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or reg,reg,reg2
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const reg2,__29027Mode
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consth reg2,__29027Mode
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store 0,0,reg,reg2
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add reg2,reg2,4
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load 0,0,reg2,reg2
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cp_write_mode reg2,reg
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.else
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mfsr reg,FPE
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andn reg,reg,FPE_FPRND_MASK
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const reg2,mode
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sll reg2,reg2,FPE_FPRND_POSITION
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or reg,reg,reg2
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mtsr FPE,reg
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.endif
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.endm
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;
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;
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; NOTE: The 29027 is the floating point coprocessor for the 29000.
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; It contains 8 floating point registers FP0 to FP7. Three of
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; these, FP0, FP1, and FP2, are currently designated as scratch,
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; that is, they will not be preserved across calls. The other
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; five contain values that must be saved whenever they are used
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; in code, and restored before the exit of the routine. The 29027
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; registers are tagged with a single bit indicating the precision
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; of the current value. When numbers are read into the 29027,
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; they are always stored in double precision, so that single
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; precision values are converted on input. Only the MOVE instruction
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; fails to do this automatic widening. If the result from calculations
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; in the 29027 ALU (determined by the result precision bit in the
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; instruction word) is to be single precision and the result saved in
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; an FP reg, the result precision bit from the instruction gets copied
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; into the precision bit for the register. If a single precision
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; SNaN is saved from the 29027, it will be converted to a double
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; precision QNaN. Along the way it will cause an unmasked exception
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; when read off the chip and cause changes to the status register.
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; So the preservation routine will need to modify the mode register to
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; mask off the exceptions, save the state of the status register before
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; saving the FP regs, and restore the status and mode registers to their
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; original settings when the save is complete.
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;
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; REFERENCE: The instructions to drive the Am29027 are described in the
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; Am29027 manual beginning on page 17. Table 4 describes the
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; operation codes and table 3 the multiplexer codes. Communication
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; with the 29000 is described on pages 11 and 12 of the Am29027
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; manual and chapters 6 and 8 of the Am29000 User's Manual
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;
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; MACRO NAME: save_FP_regs
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;
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; FUNCTION: to save the AMD 29027 floating point register values in the
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; 29000 general purpose registers
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;
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; INPUT PARAMETERS: fp_register, one of the 29027 registers FP3 - FP7
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;
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; REGISTER USAGE: the following registers are used in save_FP_regs
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;
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; rtn0 this register is used in setting the mode and status registers
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; rtn1 this register is used in setting the mode and status registers
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; rtn6 this register is used to store the MSW when FP3 is saved
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; rtn7 this register is used to store the LSW when FP3 is saved
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; rtn8 this register is used to store the MSW when FP4 is saved
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; rtn9 this register is used to store the LSW when FP4 is saved
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;
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.macro save_FP_regs,fp_register
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.ifdef _29027_MODE
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;
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; For 29027 mode, expand the macro into 29027 code to preserve FP register
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;
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.ifeqs "@fp_register@","FP3"
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const rtn6,__29027Mode ; Load the address of FP mode
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consth rtn6,__29027Mode
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load 0,0,rtn0,rtn6 ; Load MSW of FP mode into rtn0
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add rtn6,rtn6,4 ; Increment rtn6 + 4
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load 0,0,rtn1,rtn6 ; Load LSW of FP mode into rtn1
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const rtn6,CP_RESERVED_OP_EXCP_MASK ; Load mask to disable exception
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consth rtn6,CP_RESERVED_OP_EXCP_MASK
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or rtn0,rtn0,rtn6 ; OR in disable of exception mask
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cp_write_mode rtn1, rtn0 ; Reset mode w/exception disabled
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cp_read_status rtn0 ; Read status and save in rtn1
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const rtn6,CP_PASS_P | CP_P_EQ_RF3 ; Instruction is PASS_P from RF3
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consth rtn6,CP_PASS_P | CP_P_EQ_RF3
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; Load & execute the instruction
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;
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store 1,CP_WRITE_INST | CP_START,rtn6,rtn6
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load 1,CP_READ_MSBS,rtn6,rtn6 ; Read the MSW to first register
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load 1,CP_READ_LSBS,rtn7,rtn7 ; Read the LSW to second register
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cp_write_status rtn0 ; Restore the original status
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const rtn1,__29027Mode ; Load the address of FP mode
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consth rtn1,__29027Mode
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load 0,0,rtn0,rtn1 ; Load MSW of FP mode into rtn0
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add rtn1,rtn1,4 ; Increment rtn6 to __29027Mode+4
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load 0,0,rtn1,rtn1 ; Load LSW of FP mode into rtn1
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cp_write_mode rtn1, rtn0 ; Restore the original write mode
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.endif
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.ifeqs "@fp_register@","FP4"
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const rtn8,__29027Mode ; Load the address of FP mode
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consth rtn8,__29027Mode
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load 0,0,rtn0,rtn8 ; Load MSW of FP mode into rtn0
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add rtn8,rtn8,4 ; Increment rtn6 + 4
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load 0,0,rtn1,rtn8 ; Load LSW of FP mode into rtn1
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const rtn8,CP_RESERVED_OP_EXCP_MASK ; Load mask to disable exception
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consth rtn8,CP_RESERVED_OP_EXCP_MASK
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or rtn0,rtn0,rtn8 ; OR in disable of exception mask
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cp_write_mode rtn1, rtn0 ; Reset mode w/exception disabled
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cp_read_status rtn0 ; Read status and save in rtn1
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const rtn8,CP_PASS_P | CP_P_EQ_RF4 ; Instruction is PASS_P from RF4
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consth rtn8,CP_PASS_P | CP_P_EQ_RF4
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; Load & execute the instruction
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;
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store 1,CP_WRITE_INST | CP_START,rtn8,rtn8
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load 1,CP_READ_MSBS,rtn8,rtn8 ; Read the MSW to first register
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load 1,CP_READ_LSBS,rtn9,rtn9 ; Read the LSW to second register
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cp_write_status rtn0 ; Restore the original status
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const rtn1,__29027Mode ; Load the address of FP mode
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consth rtn1,__29027Mode
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load 0,0,rtn0,rtn1 ; Load MSW of FP mode into rtn0
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add rtn1,rtn1,4 ; Increment rtn6 + 4
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load 0,0,rtn1,rtn1 ; Load LSW of FP mode into rtn1
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cp_write_mode rtn1, rtn0 ; Restore the original write mode
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.endif
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.else
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;
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; For 29000 mode, do nothing
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;
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.endif
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.endm
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;
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; MACRO NAME: restore_FP_regs
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;
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; FUNCTION: to restore the AMD 29027 floating point register values from the
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; 29000 general purpose registers
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;
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; INPUT PARAMETERS: fp_register, one of the 29027 registers FP3 - FP7
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;
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; REGISTER USAGE: the following registers are used in restore_FP_regs
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;
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; rtn0 this register is used in setting the mode and status registers
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; rtn6 the value in this register is stored as the MSW of FP3
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; rtn7 the value in this register is stored as the LSW of FP3
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; rtn8 the value in this register is stored as the MSW of FP4
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; rtn9 the value in this register is stored as the LSW of FP4
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;
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.macro restore_FP_regs,fp_register
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.ifdef _29027_MODE
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;
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; For 29027 mode, move data from return registers to the correct FP register
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;
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.ifeqs "@fp_register@","FP3"
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store 1,CP_WRITE_R ,rtn6,rtn7 ; Move the data to the R register
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; Then create the instruction
|
|
;
|
|
const rtn0,CP_MOVE_P|CP_D_D|CP_P_EQ_R|CP_DEST_EQ_RF3
|
|
consth rtn0,CP_MOVE_P|CP_D_D|CP_P_EQ_R|CP_DEST_EQ_RF3
|
|
;
|
|
; Perform the write
|
|
;
|
|
store 1,(CP_WRITE_INST | CP_START),rtn0,0
|
|
.endif
|
|
.ifeqs "@fp_register@","FP4"
|
|
store 1,CP_WRITE_R ,rtn8,rtn9 ; Move the data to the R register
|
|
; Then create the instruction
|
|
;
|
|
const rtn0,CP_MOVE_P|CP_D_D|CP_P_EQ_R|CP_DEST_EQ_RF4
|
|
consth rtn0,CP_MOVE_P|CP_D_D|CP_P_EQ_R|CP_DEST_EQ_RF4
|
|
;
|
|
; Perform the write
|
|
;
|
|
store 1,(CP_WRITE_INST | CP_START),rtn0,0
|
|
.endif
|
|
.else
|
|
;
|
|
; For 29000 mode, do nothing.
|
|
;
|
|
.endif
|
|
.endm
|
|
;
|
|
; end of file intrinsi.h
|