531 lines
18 KiB
ArmAsm
531 lines
18 KiB
ArmAsm
/* Copyright (c) 2005-2013 ARM Ltd. All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions
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are met:
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1. Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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3. The name of the company may not be used to endorse or promote
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products derived from this software without specific prior written
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permission.
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THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED
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WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
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TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
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/* This file gives a basic initialisation of a Cortex-A series core. It is
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the bare minimum required to get Cortex-A core running with a semihosting
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interface.
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It sets up a basic 1:1 phsyical address to virtual address mapping;
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turns the MMU on; enables branch prediction; activates any integrated
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caches; enables the Advanced SIMD and VFP co-processors; and installs
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basic exception handlers.
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It does not handle peripherals, and assumes all memory is Normal.
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It does not change processor state from the startup privilege and security
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level.
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This has only been tested to work in ARM state.
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By default it assumes exception vectors are located from address 0.
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However, if this is not true they can be moved by defining the
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_rdimon_vector_base symbol. For example if you have HIVECS enabled you
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may pass --defsym _rdimon_vector_base=0xffff0000 on the linker command
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line. */
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/* __ARM_ARCH_PROFILE is defined from GCC 4.8 onwards, however __ARM_ARCH_7A
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has been defined since 4.2 onwards, which is when v7-a support was added
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and hence 'A' profile support was added in the compiler. Allow for this
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file to be built with older compilers. */
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#if defined(__ARM_ARCH_7A__) || (__ARM_ARCH_PROFILE == 'A')
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.syntax unified
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.arch armv7-a
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.arm
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@ CPU Initialisation
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.globl _rdimon_hw_init_hook
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.type _rdimon_hw_init_hook, %function
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_rdimon_hw_init_hook:
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@ Only run the code on CPU 0 - otherwise spin
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mrc 15, 0, r4, cr0, cr0, 5 @ Read MPIDR
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ands r4, r4, #15
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spin:
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bne spin
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mov r10, lr @ Save LR for final return
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#ifdef __ARMEB__
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@ Setup for Big Endian
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setend be
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mrc 15, 0, r4, cr1, cr0, 0 @ Read SCTLR
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orr r4, r4, #(1<<25) @ Switch to Big Endian (Set SCTLR.EE)
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mcr 15, 0, r4, cr1, cr0, 0 @ Write SCTLR
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#else
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@ Setup for Little Endian
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setend le
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mrc 15, 0, r4, cr1, cr0, 0 @ Read SCTLR
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bic r4, r4, #(1<<25) @ Switch to LE (unset SCTLR.EE)
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mcr 15, 0, r4, cr1, cr0, 0 @ Write SCTLR
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#endif
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bl is_a15_a7
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@ For Cortex-A15 and Cortex-A7 only:
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@ Write zero into the ACTLR to turn everything on.
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itt eq
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moveq r4, #0
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mcreq 15, 0, r4, c1, c0, 1
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isb
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@ For Cortex-A15 and Cortex-A7 only:
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@ Set ACTLR:SMP bit before enabling the caches and MMU,
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@ or performing any cache and TLB maintenance operations.
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ittt eq
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mrceq 15, 0, r4, c1, c0, 1 @ Read ACTLR
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orreq r4, r4, #(1<<6) @ Enable ACTLR:SMP
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mcreq 15, 0, r4, c1, c0, 1 @ Write ACTLR
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isb
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@ Setup for exceptions being taken to Thumb/ARM state
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mrc 15, 0, r4, cr1, cr0, 0 @ Read SCTLR
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#if defined(__thumb__)
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orr r4, r4, #(1 << 30) @ Enable SCTLR.TE
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#else
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bic r4, r4, #(1 << 30) @ Disable SCTLR.TE
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#endif
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mcr 15, 0, r4, cr1, cr0, 0 @ Write SCTLR
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bl __reset_caches
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mrc 15, 0, r4, cr1, cr0, 0 @ Read SCTLR
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orr r4, r4, #(1<<22) @ Enable unaligned mode
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bic r4, r4, #2 @ Disable alignment faults
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bic r4, r4, #1 @ Disable MMU
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mcr 15, 0, r4, cr1, cr0, 0 @ Write SCTLR
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mov r4, #0
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mcr 15, 0, r4, cr8, cr7, 0 @ Write TLBIALL - Invaliidate unified
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@ TLB
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@ Setup MMU Primary table P=V mapping.
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mvn r4, #0
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mcr 15, 0, r4, cr3, cr0, 0 @ Write DACR
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mov r4, #0 @ Always use TTBR0, no LPAE
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mcr 15, 0, r4, cr2, cr0, 2 @ Write TTBCR
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adr r4, page_table_addr @ Load the base for vectors
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ldr r4, [r4]
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add r4, r4, #1 @ Page tables inner cacheable
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mcr 15, 0, r4, cr2, cr0, 0 @ Write TTBR0
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mov r0, #34 @ 0x22 @ TR0 and TR1 - normal memory
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orr r0, r0, #(1 << 19) @ Shareable
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mcr 15, 0, r0, cr10, cr2, 0 @ Write PRRR
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movw r0, #0x33
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movt r0, #0x33
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mcr 15, 0, r0, cr10, cr2, 1 @ Write NMRR
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mrc 15, 0, r0, cr1, cr0, 0 @ Read SCTLR
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bic r0, r0, #(1 << 28) @ Clear TRE bit
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mcr 15, 0, r0, cr1, cr0, 0 @ Write SCTLR
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@ Now install the vector code - we move the Vector code from where it is
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@ in the image to be based at _rdimon_vector_base. We have to do this copy
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@ as the code is all PC-relative. We actually cheat and do a BX <reg> so
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@ that we are at a known address relatively quickly and have to move as
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@ little code as possible.
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mov r7, #(VectorCode_Limit - VectorCode)
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adr r5, VectorCode
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adr r6, vector_base_addr @ Load the base for vectors
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ldr r6, [r6]
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copy_loop: @ Do the copy
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ldr r4, [r5], #4
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str r4, [r6], #4
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subs r7, r7, #4
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bne copy_loop
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mrc 15, 0, r4, cr1, cr0, 0 @ Read SCTLR
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bic r4, r4, #0x1000 @ Disable I Cache
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bic r4, r4, #4 @ Disable D Cache
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orr r4, r4, #1 @ Enable MMU
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bic r4, r4, #(1 << 28) @ Clear TRE bit
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mcr 15, 0, r4, cr1, cr0, 0 @ Write SCTLR
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mrc 15, 0, r4, cr1, cr0, 2 @ Read CPACR
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orr r4, r4, #0x00f00000 @ Turn on VFP Co-procs
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bic r4, r4, #0x80000000 @ Clear ASEDIS bit
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mcr 15, 0, r4, cr1, cr0, 2 @ Write CPACR
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isb
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mov r4, #0
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mcr 15, 0, r4, cr7, cr5, 4 @ Flush prefetch buffer
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mrc 15, 0, r4, cr1, cr0, 2 @ Read CPACR
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ubfx r4, r4, #20, #4 @ Extract bits [20, 23)
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cmp r4, #0xf @ If not all set then the CPU does not
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itt eq @ have FP or Advanced SIMD.
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moveq r4, #0x40000000 @ Enable FP and Advanced SIMD
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mcreq 10, 7, r4, cr8, cr0, 0 @ vmsr fpexc, r4
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skip_vfp_enable:
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bl __enable_caches @ Turn caches on
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bx r10 @ Return to CRT startup routine
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@ This enable us to be more precise about which caches we want
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init_cpu_client_enable_dcache:
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init_cpu_client_enable_icache:
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mov r0, #1
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bx lr
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vector_base_addr:
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.word _rdimon_vector_base
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.weak _rdimon_vector_base
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page_table_addr:
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.word page_tables
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@ Vector code - must be PIC and in ARM state.
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VectorCode:
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b vector_reset
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b vector_undef
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b vector_swi
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b vector_prefetch
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b vector_dataabt
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b vector_reserved
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b vector_irq
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b vector_fiq
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vector_reset:
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adr sp, vector_sp_base
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push {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, lr}
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mov r4, #0
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b vector_common
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vector_undef:
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adr sp, vector_sp_base
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push {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, lr}
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mov r4, #1
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b vector_common
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vector_swi:
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adr sp, vector_sp_base
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push {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, lr}
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mov r4, #2
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b vector_common
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vector_prefetch:
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adr sp, vector_sp_base
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push {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, lr}
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mov r4, #3
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b vector_common
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vector_dataabt:
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adr sp, vector_sp_base
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push {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, lr}
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mov r4, #4
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b vector_common
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vector_reserved:
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adr sp, vector_sp_base
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push {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, lr}
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mov r4, #5
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b vector_common
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vector_irq:
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adr sp, vector_sp_base
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push {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, lr}
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mov r4, #6
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b vector_common
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vector_fiq:
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adr sp, vector_sp_base
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push {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip, lr}
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mov r4, #7
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b vector_common
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vector_common:
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adr r1, vector_common_adr @ Find where we're going to
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ldr r1, [r1]
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bx r1 @ And branch there
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vector_common_adr:
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.word vector_common_2 @ Common handling code
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@ Vector stack
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.p2align 3 @ Align to 8 byte boundary boundary to
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@ keep ABI compatibility
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.fill 32, 4, 0 @ 32-entry stack is enough for vector
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@ handlers.
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vector_sp_base:
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VectorCode_Limit:
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@ End of PIC code for vectors
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@ Common Handling of vectors
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.type vector_common_2, %function
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vector_common_2:
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mrs r1, APSR
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mrs r2, SPSR
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push {r1, r2} @ Save PSRs
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@ Output the vector we have caught
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bl out_nl
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adr r0, which_vector
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bl out_string
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adr r0, vector_names
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mov r1, #11
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mla r0, r4, r1, r0
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bl out_string
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bl out_nl
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@ Dump the registers
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adrl r6, register_names
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mov r7, #0
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dump_r_loop:
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mov r0, r6
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bl out_string
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add r6, r6, #6
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ldr r0, [sp, r7, lsl #2]
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bl out_word
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bl out_nl
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add r7, r7, #1
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cmp r7, #16
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blt dump_r_loop
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adr r0, end
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bl out_string
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@ And exit
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mov r0, #24
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orr r1, r4, #0x20000
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svc 0x00123456
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@ Output the string in r0
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out_string:
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push {lr}
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mov r1, r0
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mov r0, #4
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svc 0x00123456
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pop {pc}
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@ Output a New-line
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out_nl:
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mov r0, #10
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@ Fallthrough
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@ Output the character in r0
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out_char:
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push {lr}
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strb r0, [sp, #-4]!
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mov r0, #3
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mov r1, sp
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svc 0x00123456
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add sp, sp, #4
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pop {pc}
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@ Output the value of r0 as a hex-word
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out_word:
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push {r4, r5, r6, lr}
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mov r4, r0
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mov r5, #28
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adr r6, hexchars
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word_loop:
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lsr r0, r4, r5
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and r0, r0, #15
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ldrb r0, [r6, r0]
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bl out_char
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subs r5, r5, #4
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bpl word_loop
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pop {r4, r5, r6, pc}
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hexchars:
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.ascii "0123456789abcdef"
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which_vector:
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.asciz "Hit vector:"
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end:
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.asciz "End.\n"
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vector_names:
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.asciz "reset "
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.asciz "undef "
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.asciz "swi "
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.asciz "prefetch "
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.asciz "data abort"
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.asciz "reserved "
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.asciz "irq "
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.asciz "fiq "
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register_names:
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.asciz "apsr "
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.asciz "spsr "
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.asciz "r0 "
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.asciz "r1 "
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.asciz "r2 "
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.asciz "r3 "
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.asciz "r4 "
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.asciz "r5 "
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.asciz "r6 "
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.asciz "r7 "
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.asciz "r8 "
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.asciz "r9 "
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.asciz "r10 "
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.asciz "r11 "
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.asciz "r12 "
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.asciz "r14 "
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.p2align 3
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@ Enable the caches
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__enable_caches:
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mov r0, #0
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mcr 15, 0, r0, cr8, cr7, 0 @ Invalidate all unified-TLB
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mov r0, #0
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mcr 15, 0, r0, cr7, cr5, 6 @ Invalidate branch predictor
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mrc 15, 0, r4, cr1, cr0, 0 @ Read SCTLR
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orr r4, r4, #0x800 @ Enable branch predictor
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mcr 15, 0, r4, cr1, cr0, 0 @ Set SCTLR
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mov r5, lr @ Save LR as we're going to BL
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mrc 15, 0, r4, cr1, cr0, 0 @ Read SCTLR
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bl init_cpu_client_enable_icache
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cmp r0, #0
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it ne
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orrne r4, r4, #0x1000 @ Enable I-Cache
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bl init_cpu_client_enable_dcache
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cmp r0, #0
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it ne
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orrne r4, r4, #4
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mcr 15, 0, r4, cr1, cr0, 0 @ Enable D-Cache
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bx r5 @ Return
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__reset_caches:
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mov ip, lr @ Save LR
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mov r0, #0
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mcr 15, 0, r0, cr7, cr5, 6 @ Invalidate branch predictor
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mrc 15, 0, r6, cr1, cr0, 0 @ Read SCTLR
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mrc 15, 0, r0, cr1, cr0, 0 @ Read SCTLR!
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bic r0, r0, #0x1000 @ Disable I cache
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mcr 15, 0, r0, cr1, cr0, 0 @ Write SCTLR
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mrc 15, 1, r0, cr0, cr0, 1 @ Read CLIDR
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tst r0, #3 @ Harvard Cache?
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mov r0, #0
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it ne
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mcrne 15, 0, r0, cr7, cr5, 0 @ Invalidate Instruction Cache?
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mrc 15, 0, r1, cr1, cr0, 0 @ Read SCTLR (again!)
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orr r1, r1, #0x800 @ Enable branch predictor
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@ If we're not enabling caches we have
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@ no more work to do.
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bl init_cpu_client_enable_icache
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cmp r0, #0
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it ne
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orrne r1, r1, #0x1000 @ Enable I-Cache now -
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@ We actually only do this if we have a
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@ Harvard style cache.
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it eq
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bleq init_cpu_client_enable_dcache
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itt eq
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cmpeq r0, #0
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beq Finished1
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mcr 15, 0, r1, cr1, cr0, 0 @ Write SCTLR (turn on Branch predictor & I-cache)
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mrc 15, 1, r0, cr0, cr0, 1 @ Read CLIDR
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ands r3, r0, #0x7000000
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lsr r3, r3, #23 @ Total cache levels << 1
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beq Finished1
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mov lr, #0 @ lr = cache level << 1
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Loop11:
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mrc 15, 1, r0, cr0, cr0, 1 @ Read CLIDR
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add r2, lr, lr, lsr #1 @ r2 holds cache 'set' position
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lsr r1, r0, r2 @ Bottom 3-bits are Ctype for this level
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and r1, r1, #7 @ Get those 3-bits alone
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cmp r1, #2
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blt Skip1 @ No cache or only I-Cache at this level
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mcr 15, 2, lr, cr0, cr0, 0 @ Write CSSELR
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mov r1, #0
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isb sy
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mrc 15, 1, r1, cr0, cr0, 0 @ Read CCSIDR
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and r2, r1, #7 @ Extract line length field
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add r2, r2, #4 @ Add 4 for the line length offset (log2 16 bytes)
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movw r0, #0x3ff
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ands r0, r0, r1, lsr #3 @ r0 is the max number on the way size
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clz r4, r0 @ r4 is the bit position of the way size increment
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movw r5, #0x7fff
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ands r5, r5, r1, lsr #13 @ r5 is the max number of the index size (right aligned)
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Loop21:
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mov r7, r0 @ r7 working copy of max way size
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Loop31:
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orr r1, lr, r7, lsl r4 @ factor in way number and cache number
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orr r1, r1, r5, lsl r2 @ factor in set number
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tst r6, #4 @ D-Cache on?
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ite eq
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mcreq 15, 0, r1, cr7, cr6, 2 @ No - invalidate by set/way
|
|
mcrne 15, 0, r1, cr7, cr14, 2 @ yes - clean + invalidate by set/way
|
|
subs r7, r7, #1 @ Decrement way number
|
|
bge Loop31
|
|
subs r5, r5, #1 @ Decrement set number
|
|
bge Loop21
|
|
Skip1:
|
|
add lr, lr, #2 @ increment cache number
|
|
cmp r3, lr
|
|
bgt Loop11
|
|
Finished1:
|
|
@ Now we know the caches are clean we can:
|
|
mrc 15, 0, r4, cr1, cr0, 0 @ Read SCTLR
|
|
bic r4, r4, #4 @ Disable D-Cache
|
|
mcr 15, 0, r4, cr1, cr0, 0 @ Write SCTLR
|
|
mov r4, #0
|
|
mcr 15, 0, r4, cr7, cr5, 6 @ Write BPIALL
|
|
|
|
bx ip @ Return
|
|
|
|
@ Set Z if this is a Cortex-A15 or Cortex_A7
|
|
@ Other flags corrupted
|
|
is_a15_a7:
|
|
mrc 15, 0, r8, c0, c0, 0
|
|
movw r9, #0xfff0
|
|
movt r9, #0xff0f
|
|
and r8, r8, r9
|
|
movw r9, #0xc0f0
|
|
movt r9, #0x410f
|
|
cmp r8, r9
|
|
movw r9, #0xc070
|
|
movt r9, #0x410f
|
|
it ne
|
|
cmpne r8, r9
|
|
bx lr
|
|
|
|
@ Descriptor type: Section
|
|
@ Bufferable: True
|
|
@ Cacheable: True
|
|
@ Execute Never: False
|
|
@ Domain: 0
|
|
@ Impl. Defined: 0
|
|
@ Access: 0/11 Full access
|
|
@ TEX: 001
|
|
@ Shareable: False
|
|
@ Not Global: False
|
|
@ Supersection: False
|
|
#define PT(X) \
|
|
.word X;
|
|
#define PT2(X) \
|
|
PT(X) PT(X + 0x100000) PT(X + 0x200000) PT(X + 0x300000)
|
|
#define PT3(X) \
|
|
PT2(X) PT2(X + 0x400000) PT2(X + 0x800000) PT2(X + 0xc00000)
|
|
#define PT4(X) \
|
|
PT3(X) PT3(X + 0x1000000) PT3(X + 0x2000000) PT3(X + 0x3000000)
|
|
#define PT5(X) \
|
|
PT4(X) PT4(X + 0x4000000) PT4(X + 0x8000000) PT4(X + 0xc000000)
|
|
#define PT6(X) \
|
|
PT5(X) PT5(X + 0x10000000) PT5(X + 0x20000000) PT5(X + 0x30000000)
|
|
#define PT7(X) \
|
|
PT6(X) PT6(X + 0x40000000) PT6(X + 0x80000000) PT6(X + 0xc0000000)
|
|
|
|
.section page_tables_section, "aw", %progbits
|
|
.p2align 14
|
|
page_tables:
|
|
PT7(0x1c0e)
|
|
|
|
#endif //#if defined(__ARM_ARCH_7A__) || __ARM_ARCH_PROFILE == 'A'
|