The current SYS_EXIT has a bug that when making the call it always uses
the v2 calling convention. This is undefined behavior according to the
semihosting specification:
https://developer.arm.com/docs/100863/latest/semihosting-operations/sys_exit-0x18
This patch fixes it by making sure v1 passes the argument directly in the register instead
of in a block. And for v2 it does the same if the v2 extension isn't supported.
The sequence generated now is
12424: ebfffecd bl 11f60 <_has_ext_exit_extended>
12428: e3500000 cmp r0, #0
1242c: 11a0500d movne r5, sp
12430: 059d5000 ldreq r5, [sp]
12434: e1a00004 mov r0, r4
12438: e1a01005 mov r1, r5
1243c: ef00f000 svc 0x0000f000
Signed-off-by: Tamar Christina <tamar.christina@arm.com>
Semihosting v2 changes are documented here:
https://developer.arm.com/docs/100863/latest/
The biggest change is the addition of an extensions mechanism
to add more extensions in the future.
Signed-off-by: Tamar Christina <tamar.christina@arm.com>
This uses the new recursive build target in multi-build.in
The new spec files are:
For AArch32/ARM (m for mixed mode):
- rdimon-v2m.specs
- aprofile-validation-v2m.specs
- aprofile-ve-v2m.specs
These spec files will be using the new libraries generated
by multi-build.in.
Signed-off-by: Tamar Christina <tamar.christina@arm.com>
When simulating arm code, the target program startup code (crt0) uses
semihosting invocations to get the command line from the simulator. The
simulator returns the command line and its size into the area passed in
parameter. (ARM 32-bit specifications :
http://infocenter.arm.com/help/topic/com.arm.doc.dui0058d/DUI0058.pdf
chapter "5.4.19 SYS_GET_CMDLINE").
The memory area pointed by the semihosting register argument is located
in .text section (usually not writtable (RX)).
If we run this code on a simulator that respects this rights properties
(qemu user-mode for instance), the command line will not be written to
the .text program memory, in particular the length of the string. The
program runs with an empty command line. This problem hasn't been seen
earlier probably because qemu user-mode is not so much used, but this can
happen with another simulator that refuse to write in a read-only segment.
With this modification, the command line can be correctly passed to the
target program.
Changes:
- libgloss/arm/crt0.S : Arguments passed to the AngelSWI_Reason_GetCmdLine
semihosting invocation are placed into .data section instead of .text
- libgloss/aarch64/crt0.S : Idem for aarch64 AngelSVC_Reason_GetCmdLine
semihosting.
ARM EABI toolchains can optionally use the "hf" suffix to identify
hardware floating point support. Use the "*-*-eabi*" pattern to match
these toolchains.
Original patch by Bryan Hundven for the Crosstool-NG project. Improved
by Alexey Neyman.
Signed-off-by: Carlos Santos <casantos@datacom.ind.br>
CC: Bryan Hundven <bryanhundven@gmail.com
CC: Alexey Neyman <stilor@att.net>
The changes in af272aca59 only works when
using gcc/g++ with -E or -save-temps, otherwise newlib's newlib.h gets
used even if -specs=nano.specs is specified. This is because the driver
only use cpp_options spec for the external cpp tool, not for the
integrated one.
This patch uses instead cpp_unique_options which is used in all cases:
it is used directly when the integrated preprocessor is used, and
indirectly by expansion of cpp_options otherwise.
Hi,
The changes in c028685518 to use
newlib-nano's include directory work for cc1 but not cc1plus. cc1plus
comes with its own cpp spec which does not have a name attached to it.
This patch uses the renaming trick on cpp_options instead of cpp, as
cpp_options is used both by cc1 and cc1plus.
While running tests on internal systems, we identified an issue in the
startup code for newlib on AArch32 systems with Multiprocessor
Extensions to the architecture.
The issue is we were configuring page table flags to be Inner
cacheable/Outer non-cacheable, while for at least architectures with
Multiprocessor Extension, we'd configure it to Inner/Outer write-back, no
write-allocate, and cacheable.
The attached patch fixes this, and no regression on arm-none-eabi
bare-metal tests.
Adopted suggestion given by Richard offline to avoid using jump.
libgloss/
* arm/cpu-init/rdimon-aem.S: Set TTBR0 to inner/outer
cacheable WB, and no allocate on WB for arch with multiprocessor
extension.
libgloss:
* arm/Makefile.in: Add newlib/libc/machine/arm to the include path if
newlib is present.
* arm/arm.h: Include acle-compat.h.
(THUMB_V7_V6M): Rename to ...
(PREFER_THUMB): This. Use ACLE macros __ARM_ARCH_ISA_ARM instead of
__ARM_ARCH_6M__ to decide whether to define it.
(THUMB1_ONLY): Define for Thumb-1 only targets.
(THUMB_V7M_V6M): Rename to ...
(THUMB_VXM): This. Defined based on __ARM_ARCH_ISA_ARM, excluding
ARMv7.
* arm/crt0.S: Use THUMB1_ONLY rather than __ARM_ARCH_6M__,
!__ARM_ARCH_ISA_ARM rather than THUMB_V7M_V6M for fp enabling, and
PREFER_THUMB rather than THUMB_V7_V6M. Rename other occurences of
THUMB_V7M_V6M to THUMB_VXM.
* arm/linux-crt0.c: Likewise.
* arm/redboot-crt0.S: Likewise.
* arm/swi.h: Likewise.
* arm/trap.S: Likewise.
newlib:
* libc/machine/arm/memcpy-stub.c: Use ACLE macros __ARM_ARCH_ISA_THUMB
and __ARM_ARCH_ISA_ARM to check for Thumb-2 only targets rather than
__ARM_ARCH and __ARM_ARCH_PROFILE.
* libc/machine/arm/memcpy.S: Likewise.
* libc/machine/arm/setjmp.S: Likewise for Thumb-1 only target and
include acle-compat.h.
* libc/machine/arm/strcmp.S: Likewise for Thumb-1 and Thumb-2 only
target and include acle-compat.h.
* libc/sys/arm/arm.h: Include acle-compat.h.
(THUMB_V7_V6M): Rename to ...
(PREFER_THUMB): This. Use ACLE macro __ARM_ARCH_ISA_ARM instead of
__ARM_ARCH_6M__ to decide whether to define it.
(THUMB1_ONLY): Define for Thumb-1 only targets.
(THUMB_V7M_V6M): Rename to ...
(THUMB_VXM): This. Defined based on __ARM_ARCH_ISA_ARM, excluding
ARMv7.
* libc/sys/arm/crt0.S: Use PREFER_THUMB rather than THUMB_V7_V6M and
rename THUMB_V7M_V6M into THUMB_VXM.
* libc/sys/arm/swi.h: Likewise.
This header was clearly copied from the common syscall.h and customized,
but the header comment is no longer accurate -- this isn't the general
file anymore.
* arm/configure.in: Revert previous fix and change host_makefile_frag
to calculate the absolute location of srcdir/../config/default.mh.
* arm/configure: Regenerated.
* arm/cpu-init/rdimon-aem.S: Disable for M class cores.
* arm/crt0.S: Don't call _rdimon_hw_init_hook for non-A class cores.
* arm/cpu-init/Makefile.in (CPU_INIT_OBJS): Use CFLAGS.
Thomas Klein <th.r.klein@web.de>
* arm/crt0.S: Manually set the target architecture
when compiling for Thumb1 on EABI targets.
Avoid v6-only Thumb-1 MOV instruction.
2007-07-12 Daniel Jacobowitz <dan@codesourcery.com>
* arm/syscalls.c (_stat): Use _close
* arm/syscalls.c (struct poslog): Rename to...
(struct fdent): ... this.
(FILE_HANDLE_OFFSET): Remove.
(findslot): Return a struct fdent* if fd is valid, otherwise return NULL.
(newslot): New function.
(remap_handle): Remove.
(initialise_monitor_handles): Use stdout as fallback for stderr.
(wrap): Rename to...
(checkerror): ... this.
(_swiread): Use checkerror() for the return of SWI calls. Correct the use of r0.
(_read): Use findslot(). Return EBADF on bad handle.
(_swilseek): Call findslot(). Check for valid whence. Check for negative offset when using
SEEK_CUR, and check for overflow. Use checkerror(). Check *_Flen calls for errors.
(_swiwrite): Correct the use of r0.
(_write): Call findslot().
(_swiopen): Call findslot(). Check for valid flags. Use checkerror(). Call newslot().
Handle O_TRUNC, and O_WRONLY. Return index into openfiles[] for fd.
(_swiclose): Correct the use of r0.
(_close): Handle stderr == stdout case. Only reclaim handle if _swiclose succeeded.
(_getpid): Use __attribute__((unused)).
(_sbrk): Fix formatting.
(_swistat): New function.
(_stat): Call _swistat().
(_fstat): Call _swistat().
(_unlink): Correct the use of r0.
(isatty): Call finslot(). Correct the use of r0.
(_system): Call checkerror(). Correct the use of r0.
(_rename): Correct the use of r0.