7661a752ca
Annotate sparc objects with cpu hardware capabilities used.
...
bfd/
* elfxx-sparc.c (_bfd_sparc_elf_merge_private_bfd_data): New.
* elfxx-sparc.h: Declare it.
* elf32-sparc.c (elf32_sparc_merge_private_bfd_data): Call it.
* elf64-sparc.c (elf64_sparc_merge_private_bfd_data): Likewise.
binutils/
* readelf.c (display_sparc_hwcaps): New.
(display_sparc_gnu_attribute): New.
(process_sparc_specific): New.
(process_arch_specific): When EM_SPARC, EM_SPARC32PLUS,
or EM_SPARCV9 invoke process_sparc_specific.
gas/
* config/tc-sparc.c (hwcap_seen): New bitmask, defined when
not TE_SOLARIS.
(sparc_ip): When not TE_SOLARIS, accumulate hwcap bits from
sparc_opcode->flags of instruction into hwcap_seen.
(sparc_md_end): Create Tag_GNU_Sparc_HWCAPS attribute if
hwcap_seen is non-zero and not TE_SOLARIS.
gas/testsuite/
* gas/sparc/hpcvis3.s: Update for fixed fchksum16 mnemonic.
* gas/sparc/hpcvis3.d: Likewise.
include/elf/
* sparc.h (Tag_GNU_Sparc_HWCAPS): New object attribute.
(ELF_SPARC_HWCAP_*): New HWCAPS bitmask values.
include/opcode/
* sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
(F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
opcodes/
* sparc-opc.c (sparc_opcodes): Annotate table with HWCAP flag
bits. Fix "fchksm16" mnemonic.
2011-09-21 20:49:15 +00:00
1ae8302539
include/opcode/
...
* sparc.h: Document new format codes '4', '5', and '('.
(OPF_LOW4, RS3): New macros.
opcodes/
* sparc-dis.c (v9a_ast_reg_names): Add "cps".
(X_RS3): New macro.
(print_insn_sparc): Handle '4', '5', and '(' format codes.
Accept %asr numbers below 28.
* sparc-opc.c (sparc_opcodes): Add entries for HPC and VIS3
instructions.
gas/
* config/tc-sparc.c (v9a_asr_table): Add "cps".
(sparc_ip): Handle '4', '5' and '(' format codes.
gas/testsuite
* gas/sparc/hpcvis3.d: New test.
* gas/sparc/hpcvis3.s: New test source.
* gas/sparc/sparc.exp: Run new test.
2011-08-05 16:52:48 +00:00
e63d7c5914
Upgrade header files to use GPLv3
2010-04-15 10:26:09 +00:00
310932f740
Update function declarations to ISO C90 formatting
2005-07-01 11:16:27 +00:00
d699bc988f
Update the address and phone number of the FSF organization
2005-05-10 10:21:13 +00:00
61982e3c09
Convert to C90.
2003-08-07 02:25:50 +00:00
40a4eb7300
* ia64.h: Use #include "" instead of <> for local header files.
...
* sparc.h: Likewise.
2002-05-25 12:53:48 +00:00
c77e3e5481
Fix typos in ChangeLogs; add coff/external.h; fix copyright dates
2001-03-14 02:27:44 +00:00
b3c74e6dd0
gas/
...
* config/tc-sparc.c (sparc_ip): Fix a bug which caused v9_arg_p
instructions to loose any special insn->architecture mask.
* config/tc-sparc.c (v9a_asr_table): Add v9b ASRs.
(sparc_md_end, sparc_arch_types, sparc_arch,
sparc_elf_final_processing): Handle v8plusb and v9b architectures.
(sparc_ip): Handle siam mode operands. Support v9b ASRs (and
request v9b architecture if they are used).
bfd/
* elf32-sparc.c (elf32_sparc_merge_private_bfd_data,
elf32_sparc_object_p, elf32_sparc_final_write_processing):
Support v8plusb.
* elf64-sparc.c (sparc64_elf_merge_private_bfd_data,
sparc64_elf_object_p): Support v9b.
* archures.c: Declare v8plusb and v9b machines.
* bfd-in2.h: Ditto.
* cpu-sparc.c: Ditto.
include/opcode/
* sparc.h (enum sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_V9B.
Note that '3' is used for siam operand.
opcodes/
* sparc-dis.c (v9a_asr_reg_names): Add v9b ASRs.
(compute_arch_mask): Add v8plusb and v9b machines.
(print_insn_sparc): siam mode decoding, accept ASRs up to 25.
* opcodes/sparc-opc.c: Support for Cheetah instruction set.
(prefetch_table): Add #invalidate.
2000-10-20 10:38:47 +00:00
a3acbf4694
19990502 sourceware import
1999-05-03 07:29:06 +00:00
David S. Miller
Nick Clifton
Alan Modra
Jakub Jelinek
Richard Henderson