3ba05c0f92
comment typo fixes
2002-01-21 14:03:26 +00:00
d48d56d07b
[gas/ChangeLog]
...
* config/tc-ppc.c (md_parse_option): BookE is not Motorola specific.
[include/opcode/ChangeLog]
* ppc.h (PPC_OPCODE_BOOKE): BookE is not Motorola specific.
(PPC_OPCODE_BOOKE64): Likewise.
2002-01-03 02:07:19 +00:00
b346ae85d6
* hppa.h (call, ret): Move to end of table.
...
(addb, addib): PA2.0 variants should have been PA2.0W.
(ldw, ldh, ldb, stw, sth, stb, stwa): Reorder to keep disassembler
happy.
(fldw, fldd, fstw, fstd, bb): Likewise.
(short loads/stores): Tweak format specifier slightly to keep
disassembler happy.
(indexed loads/stores): Likewise.
(absolute loads/stores): Likewise.
2001-12-31 23:43:03 +00:00
bb9cc3dba0
* d10v.h (OPERAND_NOSP): New macro.
2001-12-04 10:06:40 +00:00
20a206afa2
* d10v.h (OPERAND_SP): New macro.
2001-11-29 18:03:50 +00:00
d590035529
binutils/ChangeLog
...
* doc/binutils.texi (objdump): Document ppc -M options.
gas/ChangeLog
* config/tc-ppc.c (ppc_insert_operand): Pass (ppc_cpu | ppc_size)
to operand->insert.
(md_assemble): Likewise.
gas/testsuite/ChangeLog
* gas/ppc/booke.d: Modify reloc and target matches for powerpc64.
include/opcode/ChangeLog
* ppc.h (struct powerpc_operand <insert, extract>): Add dialect param.
opcodes/ChangeLog
* ppc-opc.c (PPC64): Revert 2001-10-12. Do include PPC_OPCODE_PPC.
(insert_bat, extract_bat, insert_bba, extract_bba,
insert_bd, extract_bd, insert_bdm, extract_bdm,
insert_bdp, extract_bdp, valid_bo,
insert_bo, extract_bo, insert_boe, extract_boe,
insert_ds, extract_ds, insert_de, extract_de,
insert_des, extract_des, insert_li, extract_li,
insert_mbe, extract_mbe, insert_mb6, extract_mb6,
insert_nb, extract_nb, insert_nsi, extract_nsi,
insert_ral, insert_ram, insert_ras,
insert_rbs, extract_rbs, insert_sh6, extract_sh6,
insert_spr, extract_spr, insert_tbr, extract_tbr): Add dialect param.
(extract_bd, extract_bdm, extract_bdp,
extract_ds, extract_des,
extract_li, extract_nsi): Implement sign extension without conditional.
(insert_bdm, extract_bdm,
insert_bdp, extract_bdp, valid_bo): Handle 64 bit branch hints.
(extract_bdm, extract_bdp): Correct 32 bit validation.
(AT1_MASK, AT2_MASK): Define.
(BBOAT_MASK): Define.
(BBOATCB_MASK, BBOAT2CB_MASK, BBOATBI_MASK): Define.
(BOFM64, BOFP64, BOTM64, BOTP64): Define.
(BODNZM64, BODNZP64, BODZM64, BODZP64): Define.
(PPCCOM32, PPCCOM64): Define.
(powerpc_opcodes): Modify existing 32 bit insns with branch hints
and add new patterns to implement 64 bit branches with hints. Move
booke instructions so they match before ppc64.
* ppc-dis.c (powerpc_dialect): Set PPC_OPCODE_64 in dialect for
64 bit default targets, and parse "32" and "64" in options.
Formatting fixes.
(print_insn_powerpc): Pass dialect to operand->extract.
2001-11-15 01:08:52 +00:00
7d9961e897
Fix tic54x testsuite failures and Lmem disassembly bugs.
2001-11-13 14:22:52 +00:00
f513298e18
* i386.h (i386_optab): Add entries for "sldr", "smsw" and "str" to
...
accept WordReg.
* i386-dis.c (grps): Change "sldt", "str", and "smsw" entries
to "sldtQ", "strQ", "smswQ" respectively; all with Ev operand
category instead of Ew.
2001-11-13 01:03:55 +00:00
5088b18431
2001-11-04 Chris Demetriou <cgd@broadcom.com>
...
* mips.h (OPCODE_IS_MEMBER): Remove extra space.
2001-11-05 03:07:26 +00:00
39374014e7
Add MMIX support
2001-10-30 15:20:10 +00:00
5e709b88c5
2001-10-18 Chris Demetriou <cgd@broadcom.com>
...
* mips.h (OPCODE_IS_MEMBER): Add a no-op term to the end
of the expression, to make source code merging easier.
2001-10-18 22:41:35 +00:00
bd71a776e8
2001-10-17 Chris Demetriou <cgd@broadcom.com>
...
* mips.h: Sort coprocessor instruction argument characters
in comment, add a few more words of description for "H".
2001-10-18 01:50:26 +00:00
90cb41d9e7
[gas/testsuite/ChangeLog]
...
2001-10-17 Chris Demetriou <cgd@broadcom.com>
* gas/mips/mips.exp (sb1-ext-ps): New test to test
SB-1 core's paired-single extensions to the MIPS64 ISA.
* gas/mips/sb1-ext-ps.d: New file.
* gas/mips/sb1-ext-ps.s: New file.
[include/opcode/ChangeLog]
2001-10-17 Chris Demetriou <cgd@broadcom.com>
* mips.h (INSN_SB1): New cpu-specific instruction bit.
(OPCODE_IS_MEMBER): Allow instructions matching INSN_SB1
if cpu is CPU_SB1.
[opcodes/ChangeLog]
2001-10-17 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_isa_type): Make the ISA used to disassemble
SB-1 binaries include instructions specific to the SB-1.
* mips-opc.c (SB1): New definition.
(mips_builtin_opcodes): Add SB-1 extension opcodes "div.ps",
"recip.ps", "rsqrt.ps", and "sqrt.ps".
2001-10-18 01:42:16 +00:00
406234a70e
[gas/ChangeLog]
...
* config/tc-ppc.c (md_show_usage): Add missing -maltivec, -m7400,
-m7410, -m7450 and -m7455 options.
[gas/testsuite/ChangeLog]
* gas/ppc/altivec.s: New test for AltiVec.
* gas/ppc/altivec.d: New file.
* gas/ppc/ppc.exp: Test altivec.s
[include/opcode/ChangeLog]
* ppc.h (PPC_OPCODE_BOOKE64): Fix typo.
[opcodes/ChangeLog]
* ppc-opc.c (STRM): New AltiVec operand.
(XDSS): New AltiVec instruction form.
(mtvscr): Correct operand list.
(dst, dstt, dstst, dststt, dss, dssall): AltiVec instructions.
2001-10-17 13:13:15 +00:00
f7ab43a74f
oops, fix an error in the previous entry.
2001-10-13 02:27:25 +00:00
0cd692b40b
[gas/ChangeLog]
...
* config/tc-ppc.c (md_parse_option): New -m7410, -m7450 and -m7455
flags, equivalent to -m7400. New -maltivec to enable AltiVec
instructions. New -mbook64 and -mbooke/-mbooke32 flags to enable
64-bit and 32-bit BookE support, respectively. Change -m403 and
-m405 to set PPC403 option.
(md_show_usage): Adjust for new options.
* doc/all.texi: Set PPC.
* doc/as.texinfo: Add PPC support and pull in c-ppc.texi.
* doc/c-ppc.texi: New file.
* doc/Makefile.am (CPU_DOCS): Add c-ppc.texi.
* doc/Makefile.in: Regenerate.
[gas/testsuite/ChangeLog]
* gas/ppc/booke.s: New test for Motorola BookE.
* gas/ppc/booke.d: New file.
* gas/ppc/ppc.exp: Test booke.s.
[include/opcode/ChangeLog]
* ppc.h (PPC_OPCODE_BOOKE, PPC_OPCODE_403): New opcode flags for
BookE and PowerPC403 instructions.
[opcodes/ChangeLog]
* ppc-opc.c (insert_de, extract_de, insert_des, extract_des): New
instruction field instruction/extraction functions for new BookE
DE form instructions.
(CT): New macro for CT field in an X form instruction.
(DE, DES, DEO, DE_MASK): New macros for DE/DES fields in DE form
instructions.
(PPC64): Don't include PPC_OPCODE_PPC.
(403): New opcode macro for PPC403 processors.
(BOOKE): New opcode macro for BookE processors.
(bce, bcel, bcea, bcela, bclre, bclrel: New BookE instructions.
(bcctre, bcctrel, be, bel, bea, bela, icbt, icbte, lwzxe): Likewise.
(dcbste, lwzuxe, luxe, dcbfe, lbzxe, lwarxe, lbzuxe): Likewise.
(stwcxe, stwxe, stxe, stwuxe, stuxe, stbxe, dcbtste, stbuxe): Likewise.
(mfapidi, dcbte, lhzxe, lhzuxe, lhaxe, lhauxe, subfe64): Likewise.
(subfeo64, adde64, addeo64, sthxe, sthuxe, subfze64): Likewise.
(subfzeo64, addze64, addzeo64, dcbie, subfme64, subfmeo64): Likewise.
(addme64, addmeo64, stdcxe., mcrxr64, lwbrxe, lfsxe, lfsuxe): Likewise.
(lfdxe, lfduxe, stwbrxe, stfsxe, stfsuxe, stfdxe, dcbae): Likewise.
(stfduxe, tlbivax, tlbivaxe, lhbrxe, ldxe, lduxe, tlbsx): Likewise.
(tlbsxe, sthbrxe, stdxe, stduxe, icbie, stfiwxe, dcbze, lbze): Likewise.
(lbzue, ldue, lhze, lhzue, lhae, lhaue, lwze, lwzue): Likewise.
(stbe, stbue, sthe, sthue, stwe, stwue, lfse, lfsue, lfde): Likewise.
(lfdue, stde, stdue, stfse, stfsue, stfde, stfdue): Likewise.
* ppc-dis.c (print_insn_big_powerpc, print_insn_little_powerpc): Look
for a disassembler option of `booke', `booke32' or `booke64' to enable
BookE support in the disassembler.
2001-10-13 01:59:09 +00:00
c985580e97
Remove spurious comment
2001-09-27 07:45:32 +00:00
8d9a59afb1
fix compile time warning messages
2001-09-21 06:52:20 +00:00
60a6280984
* alpha.h (struct alpha_operand): Pack elements into bitfields.
2001-09-05 02:52:17 +00:00
a26a4cdbe0
mips3264 support
2001-08-31 21:21:54 +00:00
c2f0f4f466
* ppc.h (PPC_OPERAND_DS): Define.
2001-08-27 10:26:57 +00:00
e451b2c504
For include/opcode:
...
* d30v.h: Fix declaration of reg_name_cnt.
* d10v.h: Fix declaration of d10v_reg_name_cnt.
* arc.h: Add prototypes from opcodes/arc-opc.c.
For opcodes:
* tic54x-dis.c: Add unused attributes where needed.
* z8k-dis.c (output_instr): Add unused attribute.
* h8300-dis.c: Add missing prototypes.
(bfd_h8_disassemble): Make static.
* cris-dis.c: Add missing prototype.
* h8500-dis.c: Likewise.
* m68hc11-dis.c: Likewise.
* pj-dis.c: Likewise.
* tic54x-dis.c: Likewise.
* v850-dis.c: Likewise.
* vax-dis.c: Likewise.
* w65-dis.c: Likewise.
* z8k-dis.c: Likewise.
* d10v-dis.c: Add missing prototype.
(dis_long): Remove unused variable.
(dis_2_short): Likewise.
* sh-dis.c: Add missing prototypes.
* v850-opc.c: Likewise.
Add unused attributes where needed.
* ns32k-dis.c: Add missing prototypes.
(bit_extract_simple): Remove unused variable.
2001-08-26 11:47:39 +00:00
ab7c6379a8
Add support for MIPS R1[02]000 performance counter opcodes.
2001-08-16 19:24:33 +00:00
b5c27d80c0
Revert 2001-08-08 changes.
2001-08-10 01:34:47 +00:00
584b6591df
* ppc.h (struct powerpc_operand): New field `reloc'.
...
* ppc-opc.c: Include "bfd.h".
(powerpc_operands): Add new field for reloc type.
2001-08-08 13:19:36 +00:00
ef393a8fad
* some support for funny-endian 16/32-bit insn sets
...
[cgen/ChangeLog]
2001-07-11 Frank Ch. Eigler <fche@redhat.com>
* desc-cpu.scm (-gen-mach-table-defns): Emit fourth field: the
mach->cpu insn-chunk-bitsize.
(-gen-cpu-open): In @arch@_cgen_rebuild_tables, process above new
field toward CGEN_CPU_TABLE->insn_chunk_bitsize.
* mach.scm (<cpu>): New field insn-chunk-bitsize.
(-cpu-parse, -cpu-read): Parse/initialize it.
* doc/rtl.texi (define-cpu): Document it.
[opcodes/ChangeLog]
2001-07-11 Frank Ch. Eigler <fche@redhat.com>
* cgen-dis.in (print_insn): Use cgen_get_insn_value instead of
bfd_get_bits.
* cgen-opc.c (cgen_get_insn_value, cgen_put_insn_value): Respect
non-zero CGEN_CPU_DESC->insn_chunk_bitsize.
[include/opcode/ChangeLog]
2001-07-11 Frank Ch. Eigler <fche@redhat.com>
* cgen.h (CGEN_MACH): Add insn_chunk_bitsize field.
(cgen_cpu_desc): Ditto.
2001-07-12 02:32:25 +00:00
6e06cb0d32
2001-07-07 Ben Elliston <bje@redhat.com>
...
* m88k.h: Clean up and reformat. Remove unused code.
2001-07-06 22:14:07 +00:00
5a5f43a0b9
Index: opcodes/ChangeLog
...
2001-06-13 Geoffrey Keating <geoffk@redhat.com>
* cgen-asm.c (cgen_parse_keyword): When looking for the
boundaries of a keyword, allow any special characters
that are actually in one of the allowed keyword.
* cgen-opc.c (cgen_keyword_add): Add any special characters
to the nonalpha_chars field.
Index: cgen/ChangeLog
2001-06-13 Geoffrey Keating <geoffk@redhat.com>
* desc.scm (<keyword> 'gen-defn): Add extra zero into
CGEN_KEYWORD_ENTRY initializers.
Index: include/opcode/ChangeLog
2001-06-13 Geoffrey Keating <geoffk@redhat.com>
* cgen.h (cgen_keyword): Add nonalpha_chars field.
2001-06-14 20:38:42 +00:00
51352f8ed0
Fix some entries.
2001-05-28 10:37:50 +00:00
ffa9dc2c1c
Add MIPS r12k support
2001-05-23 17:26:39 +00:00
865cf1b95c
2001-05-23 John Healy <jhealy@redhat.com>
...
* cgen.h: Increased CGEN_MAX_SYNTAX_ELEMENTS to 48.
2001-05-23 15:34:43 +00:00
92f998d4e0
Fix MIPS disassembler so that it produces reassemblable code.
2001-05-15 12:11:12 +00:00
24a474a4aa
Correct cvtps2dq, movdq2q, movq2dq, and movq problems.
2001-05-12 09:52:39 +00:00
268fad77db
Assorted fixes to pinsrw, pextrw, pmovmskb, movmskp, maskmovq.
2001-05-04 11:10:53 +00:00
b25c2ad730
* cris.h (enum cris_insn_version_usage): Correct comment for
...
cris_ver_v3p.
2001-04-05 19:35:17 +00:00
e380bf39ff
Small tweaks to sse2 instructions.
2001-03-24 06:29:15 +00:00
21ebbf8ecf
* cris.h (ADD_PC_INCR_OPCODE): New macro.
2001-03-22 16:09:20 +00:00
10654b8555
2001-03-21 Kazu Hirata <kazu@hxi.com>
...
* h8300.h: Fix formatting.
2001-03-22 02:51:19 +00:00
46b107fb28
paddq and psubq support.
2001-03-22 02:27:53 +00:00
ca05a71296
Fix register name printed in warning message.
2001-03-19 11:28:20 +00:00
c77e3e5481
Fix typos in ChangeLogs; add coff/external.h; fix copyright dates
2001-03-14 02:27:44 +00:00
35fc781b4b
new defines for Coldfire V4.
2001-02-28 23:47:10 +00:00
72a82eaa20
Add PDP-11 support
2001-02-18 23:33:07 +00:00
343329bac2
* i386.h (i386_optab): SSE integer converison instructions have
...
64bit versions on x86-64.
* i386-dis.c (prefix_user_t): Add 'Y' to SSE ineger converison
instructions.
(putop): Handle 'Y'
2001-02-12 16:42:49 +00:00
da2da20f20
Remove extraneous whitespace
2001-02-10 22:26:55 +00:00
1e667f61b7
Add s390 support
2001-02-10 00:58:38 +00:00
30da4f3d29
Binutils portion of fix for syntax array elements when max
...
operands is greater than 127.
2001-02-02 Patrick Macdonald <patrickm@redhat.com>
* cgen.h (CGEN_SYNTAX_CHAR_TYPE): Typedef as unsigned short.
(CGEN_MAX_SYNTAX_ELEMENTS): Rename from CGEN_MAX_SYNTAX_BYTES.
(CGEN_SYNTAX): Define using CGEN_MAX_SYNTAX_ELEMENTS.
* fr30-desc.h: Regenerate with CGEN_MAX_SYNTAX_ELEMENTS.
* m32r-desc.h: Regenerate.
2001-02-02 23:04:39 +00:00
77ab85cb32
Fix swapgs instruction.
2001-01-24 07:32:34 +00:00
b0c8c95b1e
Adds assembly and dis-assembly support for the HPPA wide
...
mode, 16 bit forms of ldi, ldo, ldw and stw instructions.
2001-01-14 05:14:45 +00:00
ad3faf61ab
* i386.c (md_assemble): Check cpu_flags even for nullary instructions.
...
* i386.h (i386_optab): Fix pusha and ret templates.
* i386-dis.c (dis386_att, disx86_64_att): Fix ret, lret and iret
templates.
2001-01-13 09:05:55 +00:00
c9bd08bcb2
Updated ARC assembler from arccores.com
2001-01-11 21:20:19 +00:00
d9d921952c
* i386.h (pinsrw): Add.
...
(pshufw): Remove.
(cvttpd2dq): Fix operands.
(cvttps2dq): Likewise.
(movq2q): Rename to movdq2q.
2001-01-10 14:31:46 +00:00
c0e5a443da
Fix "movnti"
2001-01-10 00:24:43 +00:00
e24150c66b
2001-01-09 Jeff Johnston <jjohnstn@redhat.com>
...
* cgen.h (CGEN_SYNTAX_CHAR_TYPE): New typedef based on max number
of operands (unsigned char or unsigned short).
(CGEN_SYNTAX): Changed to make array CGEN_SYNTAX_CHAR_TYPE.
(CGEN_SYNTAX_CHAR): Changed to cast to unsigned char.
2001-01-09 17:01:07 +00:00
8ab2401414
* tc-i386.c (md_assemble): Handle third byte of the opcode as prefix.
...
* i386.h (i386_optab): Make [sml]fence template to use immext field.
2001-01-05 12:30:12 +00:00
234ad742b1
* tc-i386.h (CpuK6, CpuAthlon, CpuSledgehammer, CpuMMX, Cpu3dnow,
...
CpuUnknown): Renumber
(CpuP4, CpuSSE2): New.
(CpuUnknownFlags): Add CpuP4 and CpuSSE2
* i386.h (i386_optab): Fix 64bit pushf template; Add instructions
introduced by Pentium4
2001-01-03 15:36:26 +00:00
00a8972f02
* configure.in: Add support for x86_64 and x86_64-*-linux-gnu*
...
* NEWS: Add x86_64.
* i386.h (i386_optab): Add "rex*" instructions;
add swapgs; disable jmp/call far direct instructions for
64bit mode; add syscall and sysret; disable registers for 0xc6
template. Add 'q' suffixes to extendable instructions, disable
obsoletted instructions, add new sign/zero extension ones.
(i386_regtab): Add extended registers.
(*Suf): Add No_qSuf.
(q_Suf, wlq_Suf, bwlq_Suf): New.
2000-12-30 18:05:10 +00:00
8a46ccd7e2
* tc-i386.h (i386_target_format): Define even for ELFs.
...
(QWORD_MNEM_SUFFIX): New macro.
(CpuK6,CpuAthlon,CpuSledgehammer, Cpu64, CpuNo64, CpuUnknownFlags):
New macros
(CpuMMX,CpuSSE,Cpu3dnow, CpuUnknown): Renumber.
(IgnoreSize, DefaultSize, No_?Suf, FWait, IsString, regKludge, IsPrefix,
ImmExt): Renumber.
(Size64, No_qSuf, NoRex64, Rex64): New macros.
(Reg64, Imm32S, Imm64, Disp32S, Disp64): New macros.
(Imm8, Imm8S, Imm16, Imm32, Imm1, BaseIndex, Disp8, Disp16, Disp32,
InOutPortReg,ShiftCount, Control, Debug, Test, FloatReg, FloatAcc,
SReg2, SReg3, Acc, JumpAbsolute, RegMMX, RegXMM, EsSeg, InvMem): Renumber.
(Reg, WordReg): Add Reg64.
(Imm): Add Imm32S and Imm64.
(EncImm): New.
(Disp): Add Disp64 and Disp32S.
(AnyMem): Add Disp32S.
(RegRex, RegRex64): New macros.
(rex_byte): New type.
* tc-i386.c (set_16bit_code_flag): Kill.
(fits_in_unsigned_long, fits_in_signed_long): New functions.
(reloc): New parameter "signed"; support x86_64.
(set_code_flag): New.
(DEFAULT_ARCH): New macro; default to "i386".
(default_arch): New static variable.
(struct _i386_insn): New fields Operand_PCrel; rex.
(flag_16bit_code): Kill; All tests replaced to "flag_code == CODE_64BIT";
(flag_code): New enum and static variable.
(use_rela_relocations): New static variable.
(flag_code_names): New static variable.
(cpu_arch_flags): Default to CpuUnknownFlags|CpuNo64.
(cpu_arch): Add "sledgehammer"; Add CPUAthlon to Athlon and CpuK6 to
K6 and Athlon.
(i386_align_code): Return plain "nop" for x86_64.
(mode_from_disp_size): Support Disp32S.
(smallest_imm_type): Support Imm32S and Imm64.
(offset_in_range): Support size of 8.
(set_cpu_arch): Do not clobber to Cpu64/CpuNo64.
(md_pseudo_table): Add "code64"; use set_code_flat.
(md_begin): Emit sane error message on hash failure.
(tc_i386_fix_adjustable): Support x86_64 relocations.
(md_assemble): Support QWORD_MNEM_SUFFIX, REX registers,
instructions supported on particular arch just partially,
output of 64bit immediates, handling of Imm32S and Disp32S type.
(i386_immedaite): Support x86_64 relocations; support 64bit constants.
(i386_displacement): Likewise.
(i386_index_check): Cleanup; support 64bit addresses.
(md_apply_fix3): Support x86_64 relocation and rela.
(md_longopts): Add "32" and "64".
(md_parse_option): Add OPTION_32 and OPTION_64.
(i386_target_format): Call even for ELFs; choose between
elf64-x86-64 and elf32-i386.
(i386_validate_fix): Refuse GOTOFF in 64bit mode.
(tc_gen_reloc): Support rela relocations and x86_64.
(intel_e09_1): Support QWORD.
* i386.h (i386_optab): Replace "Imm" with "EncImm".
(i386_regtab): Add flags field.
2000-12-20 13:24:13 +00:00
5092a8140b
Fix Formatting.
2000-12-12 19:25:07 +00:00
294f81d78d
Add MIPS SB1 machine
2000-12-02 01:10:33 +00:00
f9fe8a8ead
Add MIPS V and MIPS 64 machine numbers
2000-12-02 00:55:22 +00:00
388732e7f6
Add MIPS32 as a seperate MIPS architecture
2000-12-01 21:35:38 +00:00
2a91907cc0
Improve MIPS32 support
2000-12-01 20:05:32 +00:00
b3c74e6dd0
gas/
...
* config/tc-sparc.c (sparc_ip): Fix a bug which caused v9_arg_p
instructions to loose any special insn->architecture mask.
* config/tc-sparc.c (v9a_asr_table): Add v9b ASRs.
(sparc_md_end, sparc_arch_types, sparc_arch,
sparc_elf_final_processing): Handle v8plusb and v9b architectures.
(sparc_ip): Handle siam mode operands. Support v9b ASRs (and
request v9b architecture if they are used).
bfd/
* elf32-sparc.c (elf32_sparc_merge_private_bfd_data,
elf32_sparc_object_p, elf32_sparc_final_write_processing):
Support v8plusb.
* elf64-sparc.c (sparc64_elf_merge_private_bfd_data,
sparc64_elf_object_p): Support v9b.
* archures.c: Declare v8plusb and v9b machines.
* bfd-in2.h: Ditto.
* cpu-sparc.c: Ditto.
include/opcode/
* sparc.h (enum sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_V9B.
Note that '3' is used for siam operand.
opcodes/
* sparc-dis.c (v9a_asr_reg_names): Add v9b ASRs.
(compute_arch_mask): Add v8plusb and v9b machines.
(print_insn_sparc): siam mode decoding, accept ASRs up to 25.
* opcodes/sparc-opc.c: Support for Cheetah instruction set.
(prefetch_table): Add #invalidate.
2000-10-20 10:38:47 +00:00
eb69b80812
Fix ia64 gas testsuite. Update ia64 DV tables. Fix ia64 gas testsuite again.
...
gas/ChangeLog
* config/tc-ia64.c (dv_sem): Add "stop".
(specify_resource, case IA64_RS_PR): Only handles regs 1 to 15 now.
(specify_resource, case IA64_RS_PRr): New for regs 16 to 62.
(specify_resource, case IA64_RS_PR63): Reorder (note == 7) test to
match above.
(mark_resources): Check IA64_RS_PRr.
gas/testsuite/ChangeLog
* gas/ia64/dv-raw-err.s: Add new testcases for PR%, 16 - 62.
* gas/ia64/dv-waw-err.s: Likewise.
* gas/ia64/dv-imply.d: Regenerate.
* gas/ia64/dv-mutex.d, gas/ia64/dv-raw-err.l, gas/ia64/dv-safe.d,
gas/ia64/dv-srlz.d, gas/ia64/dv-war-err.l, gas/ia64/dv-waw-err.l,
gas/ia64/opc-f.d, gas/ia64/opc-i.d, gas/ia64/opc-m.d: Likewise.
include/opcode/ChangeLog
* ia64.h (enum ia64_dependency_semantics): Add IA64_DVS_STOP.
opcodes/ChangeLog
* ia64-dis.c (print_insn_ia64): Revert Aug 7 byte skip count change.
* ia64-gen.c (parse_semantics): Handle IA64_DVS_STOP.
(lookup_specifier): Handle "PR%, 1 to 15" and "PR%, 16 to 62".
* ia64-ic.tbl, ia64-raw.tbl, ia64-war.tbl, ia64-waw.tbl: Update.
* ia64-asmtab.c: Regnerate.
2000-09-22 19:43:49 +00:00
67b0ce5ff0
Add support for the MIPS32
2000-09-14 01:47:37 +00:00
5be3981a24
doco addition.
2000-09-05 05:22:24 +00:00
6afcd43da0
Fix 3 DV bugs, and a few minor cleanups.
...
gas/
* config/tc-ia64.c (specify_resource, case IA64_RS_GR): Handle
postincrement modified registers. Handle IA64_OPND_R3_2 addl
source registers.
(note_register_values): Handle IA64_OPND_R3_2 operands.
gas/testsuite/
* gas/ia64/dv-raw-err.s: Add new tests for addl and postinc.
* gas/ia64/dv-raw-err.l: Likewise.
* gas/ia64/dv-waw-err.l: Update sed pattern.
* gas/ia64/opc-f.pl: Delete fpsub, and fpadd comment.
* gas/ia64/opc-f.s, gas/ia64/opc-f.d: Regenerate.
include/opcode/
* ia64.h (IA64_OPCODE_POSTINC): New.
opcodes/
* ia64-ic.tbl (pr-readers-nobr-nomovpr): Add addl, adds. Delete
break, mov-immediate, nop.
* ia64-opc-f.c: Delete fpsub instructions.
* ia64-opc-m.c: Add POSTINC to all instructions with postincrement
address operand. Rewrite using macros to avoid long lines.
* ia64-opc.h (POSTINC): Define.
* ia64-asmtab.c: Regenerate.
2000-08-16 23:20:14 +00:00
e3c9eeaf79
2000-08-15 H.J. Lu <hjl@gnu.org>
...
* i386.h: Swap the Intel syntax "movsx"/"movzx" due to the
IgnoreSize change.
2000-08-16 17:29:23 +00:00
553d0fe671
* avr.h (AVR_UNDEF_P, AVR_SKIP_P, AVR_DISP0_P): New macros.
...
Move related opcodes closer to each other.
Minor changes in comments, list undefined opcodes.
2000-08-06 14:09:14 +00:00
b58a443464
2000-07-26 Dave Brolley <brolley@redhat.com>
...
* cgen.h (cgen_hw_lookup_by_num): Second parameter is unsigned.
2000-07-26 22:44:42 +00:00
43d25e8350
cris.h: New file.
2000-07-20 15:39:41 +00:00
650536b382
Applied Marek Michalkiewicz <marekm@linux.org.pl>'s patch to ehance the AVR port.
2000-06-27 01:45:30 +00:00
8929e0a70c
Applied Stephane Carrez <Stephane.Carrez@worldnet.fr> patches to add support
...
for m68hc11 and m68hc12 processors.
2000-06-19 01:22:42 +00:00
b6c40e83e9
* avr.h: clr,lsl,rol, ... moved after add,adc, ...
2000-06-09 18:02:05 +00:00
987dd6a80f
* avr.h: New file with AVR opcodes.
2000-06-07 17:48:35 +00:00
83d485ca0c
Define the ALONE flag bit, for use in the opcode table.
2000-05-25 22:23:45 +00:00
6458314f0d
Allow d suffix on iret
2000-05-23 00:36:39 +00:00
8c1c1f1a43
Fix fild.
2000-05-17 00:47:51 +00:00
0bf4b1e8ab
* cgen/opcodes fix
...
* approved by nickc
[opcodes/ChangeLog]
2000-05-16 Frank Ch. Eigler <fche@redhat.com>
* fr30-desc.h: Partially regenerated to account for changed
CGEN_MAX_* -> CGEN_ACTUAL_MAX_* macros.
* m32r-desc.h: Ditto.
[include/opcode/ChangeLog]
2000-05-16 Frank Ch. Eigler <fche@redhat.com>
* cgen.h (CGEN_MAX_SYNTAX_BYTES): Increase to 32. Check that
it exceeds CGEN_ACTUAL_MAX_SYNTAX_BYTES, if set.
(CGEN_MAX_IFMT_OPERANDS): Increase to 16. Check that it exceeds
CGEN_ACTUAL_MAX_IFMT_OPERANDS, if set.
2000-05-16 19:28:07 +00:00
e6342d0038
Fix cpu_flags for sys{enter,exit} fx{save,restore}
2000-05-13 14:01:54 +00:00
9484bf7072
`.arch cpu_type' pseudo for x86.
2000-05-13 09:26:23 +00:00
75546193ec
Support for tic54x target.
2000-05-06 17:14:34 +00:00
cf3eb87bef
* ppc.h (PPC_OPCODE_ALTIVEC): New opcode flag for vector unit.
...
(PPC_OPERAND_VR): New operand flag for vector registers.
2000-05-03 22:19:45 +00:00
f8c723b8f8
* h8300.h (EOP): Add missing initializer.
2000-05-01 16:55:50 +00:00
2d6fec0fc1
* hppa.h (pa_opcodes): New opcodes for PA2.0 wide mode
...
forms of ld/st{b,h,w,d} and fld/fst{w,d} (16-bit displacements).
New operand types l,y,&,fe,fE,fx added to support above forms.
(pa_opcodes): Replaced usage of 'x' as source/target for
floating point double-word loads/stores with 'fx'.
Fr
2000-04-21 21:04:04 +00:00
4501dfbc42
IA-64 ELF support.
2000-04-21 20:22:23 +00:00
1b3755ec07
Fix value of SHORT_A1.
...
Move SHORT_AR to end of list of short instructions.
2000-03-27 20:17:02 +00:00
114d3d3070
Mostly cosmetic. Fixes to comments. Don't start as_bad and as_warn
...
messages with capital. Don't malign Unixware, malign SysV386 instead.
2000-03-26 14:13:01 +00:00
92976eab7d
Apply patch for 100679
2000-03-02 23:01:40 +00:00
e53d3a5d95
Extend the i386 gas testsuite to do some tests for intel_syntax. Fix all
...
the errors exposed by this addition. These were intel mode
"fi... word ptr", "fi... dword ptr", "jmp Imm seg, Imm offset", "out dx,al".
The failure with intel "out dx,al" was also present in att "out al,dx".
Extend testsuite to catch this case too.
2000-02-25 11:41:12 +00:00
7620791bd9
Rename 'flags' to 'signed_overflow_ok_p'
2000-02-24 23:57:23 +00:00
4d0ce66d1f
2000-02-24 Andrew Haley <aph@cygnus.com>
...
* cgen.h (CGEN_INSN_MACH_HAS_P): New macro.
(CGEN_CPU_TABLE): flags: new field.
Add prototypes for new functions.
2000-02-24 21:56:53 +00:00
759e2a8845
Forgot Changelog for last i386.h change.
2000-02-24 12:41:54 +00:00
58dabf5040
Add IBM 370 support.
2000-02-23 13:52:22 +00:00
196bbedaa7
g2000-02-22 Andrew Haley <aph@cygnus.com>
...
* mips.h: (OPCODE_IS_MEMBER): Add comment.
2000-02-22 19:01:25 +00:00
b7c65de2b8
ChangeLog change only.
2000-02-22 16:59:39 +00:00
95d64ccd4e
1999-12-30 Andrew Haley <aph@cygnus.com>
...
* mips.h (OPCODE_IS_MEMBER): Add gp32 arg.
2000-02-22 14:39:20 +00:00
1a80e0b5d2
Cosmetic changes to tc-i386.[ch] + extend x86 gas testsuite jmp and
...
call tests + tweak intel mode far call and jmp.
2000-01-15 12:06:03 +00:00
a3717e6ce0
x86 indirect jump/call syntax fixes. Disassembly fix for lcall.
1999-12-27 16:10:31 +00:00
488e1589f7
* mn10300.h: Add new operand types. Add new instruction formats.
1999-12-01 10:05:24 +00:00
cef484e503
* hppa.h (pa_opcodes): Correctly handle immediate for PA2.0 "bb"
...
instruction.
1999-11-25 03:28:22 +00:00
10ab31ca59
For include/opcode:
...
* mips.h (INSN_ISA5): New.
For opcodes:
* mips-opc.c (I5): New.
(abs.ps,add.ps,alnv.ps,c.COND.ps,cvt.s.pl,cvt.s.pu,cvt.ps.s
madd.ps,movf.ps,movt.ps,mul.ps,net.ps,nmadd.ps,nmsub.ps,
pll.ps,plu.ps,pul.ps,puu.ps,sub.ps,suxc1,luxc1): New.
1999-11-18 19:53:48 +00:00
7372e38bfd
For include/opcode:
...
* mips.h (OPCODE_IS_MEMBER): New.
For gas:
* config/tc-mips.c (macro_build): Use OPCODE_IS_MEMBER.
(mips_ip): Use OPCODE_IS_MEMBER.
For opcodes:
* mips-dis.c (_print_insn_mips): Use OPCODE_IS_MEMBER.
1999-11-01 19:29:55 +00:00
f1a1e10e18
Define SHORT_AR (fix for CR: 101340)
1999-10-29 09:49:04 +00:00
da516da191
Add md expression support; Cleanup alpha warnings
1999-10-18 22:29:14 +00:00
756b080175
* hppa.h (pa_opcodes): Add load and store cache control to
...
instructions. Add ordered access load and store.
* hppa.h (pa_opcode): Add new entries for addb and addib.
* hppa.h (pa_opcodes): Fix cmpb and cmpib entries.
* hppa.h (pa_opcodes): Add entries for cmpb and cmpib.
1999-10-10 07:55:25 +00:00
e1286a3825
Added seven new instructions ld, ld2w, sac, sachi, slae, st and
...
st2w for d10v. Created new testsuite for d10v to verify new
instructions.
1999-10-07 06:17:04 +00:00
1a6447612f
* hppa.h (pa_opcodes): Add "call" and "ret". Clean up "b", "bve"
...
and "be" using completer prefixes.
1999-09-23 14:29:10 +00:00
3118b34c80
* hppa.h (pa_opcodes): Add initializers to silence compiler.
1999-09-23 13:14:33 +00:00
f026123d83
* hppa.h: Update comments about character usage.
1999-09-23 13:10:07 +00:00
27421fd084
* hppa.h (pa_opcodes): Fix minor thinkos introduced while cleaning
...
up the new fstw & bve instructions.
1999-09-20 09:57:19 +00:00
9eff6c959f
* hppa.h (pa_opcodes): Add remaining PA2.0 integer load/store
...
instructions.
1999-09-19 20:05:00 +00:00
c7b64ad4f0
* hppa.h (pa_opcodes): Add remaining PA2.0 FP load/store instructions.
1999-09-19 19:43:06 +00:00
675e0509d0
* hppa.h (pa_opcodes): Add long offset double word load/store
...
instructions.
1999-09-19 19:19:50 +00:00
45faedf39e
* hppa.h (pa_opcodes): Add FLAG_STRICT variants of FP loads and
...
stores.
1999-09-19 18:54:23 +00:00
02a209f9b5
* hppa.h (pa_opcodes): Handle PA2.0 fcnv, fcmp and ftest insns.
1999-09-19 18:44:13 +00:00
4832d84f3d
* hppa.h (pa_opcodes): Finish support for PA2.0 "b" instructions.
1999-09-19 18:10:28 +00:00
af5442f198
* hppa.h (pa_opcodes): Handle PA2.0 "bve" instructions.
1999-09-19 17:39:17 +00:00
24e0770908
* hppa.h (pa_opcodes): Add new syntax "be" instructions.
1999-09-19 17:16:08 +00:00
84e7327d75
* hppa.h (pa_opcodes): Note use of 'M' and 'L'.
1999-09-19 17:12:55 +00:00
1ddec1532b
* hppa.h (pa_opcodes): Add support for "b,l".
1999-09-19 16:55:09 +00:00
4969046449
* hppa.h (pa_opcodes): Add support for "b,gate".
1999-09-19 16:41:51 +00:00
5566981684
* hppa.h (pa_opcodes): Use 'fX' for first register operand
...
in xmpyu.
1999-09-18 18:08:34 +00:00
67faa9adc2
* hppa.h (pa_opcodes): Fix mask for probe and probei.
1999-09-18 17:49:43 +00:00
578f46be35
* hppa.h (pa_opcodes): Fix mask for depwi.
1999-09-18 17:43:47 +00:00
6338a22379
* hppa.h (pa_opcodes): Add "addil" variant which has the %r1 as
...
an explicit output argument.
1999-09-07 19:46:47 +00:00
6935f65eff
* hppa.h: Add strict variants of PA1.0/PA1.1 loads and stores.
...
Add a few PA2.0 loads and store variants.
1999-09-06 10:42:11 +00:00
12ed226cc7
1999-09-04 Steve Chamberlain <sac@pobox.com>
...
* pj.h: New file.
1999-09-04 17:16:21 +00:00
a4972584a4
Allow spaces in i386 FP reg names, eg. %st ( 1 ).
1999-08-29 23:44:27 +00:00
9b2c866771
* hppa.h (pa_opcodes): Replace 'f' by 'v'. Prefix float register args
...
by 'f'.
1999-08-29 07:51:43 +00:00
b7fdf3c074
* hppa.h (pa_opcodes): Add extrd, extrw, depd, depdi, depw, depwi.
...
Add supporting args.
1999-08-28 10:58:26 +00:00
ab3ce6303a
* hppa.h: Document new completers and args.
...
* hppa.h (pa_opcodes): Add 64 bit patterns and pa2.0 syntax for uxor,
uaddcm, dcor, addi, add, sub, subi, shladd, rfi, and probe. Add pa2.0
extensions for ssm, rsm, pdtlb, pitlb. Add performance instructions
pmenb and pmdis.
1999-08-28 10:16:15 +00:00
a7192fe0ab
* hppa.h (pa_opcodes): Add pa2.0 instructions hadd, hshl,
...
hshr, hsub, mixh, mixw, permh.
1999-08-28 08:46:57 +00:00
ad9cdcce7b
* hppa.h (pa_opcodes): Change completers in instructions to
...
use 'c' prefix.
1999-08-28 08:16:55 +00:00
5193c502b0
* hppa.h (pa_opcodes): Add popbts, new forms of bb, havg,
...
hshladd, hshradd, shrpd, and shrpw instructions. Update arg comments.
1999-08-28 06:41:11 +00:00
39484d8592
* hppa.h (pa_opcodes): Change fmpyfadd, fmpynfadd, fneg,
...
fnegabs to use 'I' instead of 'F'.
1999-08-28 06:27:12 +00:00
e5af6ca113
Add AMD athlon support to x86 assembler and disassembler.
1999-08-21 12:40:35 +00:00
d0c72719e5
* cgen.h (CGEN_INSN_MACH_HAS_P): New macro.
1999-08-19 05:45:30 +00:00
85038a8a7f
* hppa.h (pa_opcodes): Add 64 bit versions of or, xor, and,
...
and andcm. Add 32 and 64 bit version of cmpclr, cmpiclr.
1999-08-06 16:03:53 +00:00
55c98dbaae
* hppa.h: Document 64 bit condition completers.
1999-08-06 15:49:29 +00:00
978c8e91e3
* hppa.h (pa_opcodes): Change condition args to use '?' prefix.
1999-08-05 22:58:08 +00:00
0274eb115d
Support for gcc to generate 16-bit i386 code. (.code16gcc)
1999-08-04 10:07:41 +00:00
83849fdd14
* hppa.h (pa_opcodes): Add "pushnom" and "pushbts".
...
* hppa.h (pa_opcodes): Mark all PA2.0 opcodes with FLAG_STRICT.
1999-07-28 10:31:15 +00:00
733df03348
* hppa.h (pa_opcodes): Change xmpyu, fmpyfadd,
...
and fmpynfadd to use 'J' and 'K' instead of 'E' and 'X'.
1999-07-28 08:06:30 +00:00
bec8046d67
o
...
include/opcode/i386.h: Add "undocumented" AMD 3DNow! pf2iw, pi2fw, pswapw
1999-07-13 07:41:46 +00:00
ca7cd5dc64
* hppa.h (struct pa_opcode): Add new field "flags".
...
(FLAGS_STRICT): Define.
1999-06-30 23:20:56 +00:00
386449a2f8
* hppa.h (pa_opcodes): Add pa2.0 clrbts instruction.
1999-06-25 03:29:45 +00:00
233881c2a2
* hppa.h (pa_opcodes): Add entries for mfia and mtsarcm instructions.
1999-06-25 03:23:12 +00:00
30b962fd67
P
...
include/opcode/i386.h: Allow bswapl, arplw, and other dodgy insns.
opcodes/i386-dis.c: Fix a comment
1999-06-23 06:00:09 +00:00
664151086b
* hppa.h (pa_opcodes): Move integer arithmetic instructions after
...
integer logical instructions.
1999-05-28 14:26:52 +00:00
6a26bbce7b
1999-05-28 Linus Nordberg <linus.nordberg@canit.se>
...
* m68k.h: Document new formats `E', `G', `H' and new places `N',
`n', `o'.
* m68k.h: Define mcf5206e, mcf5307, mcf. Document new format `u'
and new places `m', `M', `h'.
1999-05-27 22:31:03 +00:00
4b69b0a1f1
* hppa.h (pa_opcodes): Add several processor specific system
...
instructions.
1999-05-27 03:19:32 +00:00
171cdecb9f
* hppa.h (pa_opcodes): Add second entry for "comb", "comib",
...
"addb", and "addib" to be used by the disassembler.
1999-05-26 16:04:11 +00:00
4b5775a3e9
P
...
i386 PIII SIMD support, remove ReverseRegRegmem kludge
tidy a few things in i386 intel mode disassembly
1999-05-13 06:00:27 +00:00
a594afbb42
* ppc.h (PPC_OPCODE_64_BRIDGE): New.
1999-05-08 23:28:34 +00:00
a3acbf4694
19990502 sourceware import
1999-05-03 07:29:06 +00:00
Alan Modra
Matthew Green
Jeff Law
Alexandre Oliva
Tim Wall
Chris Demetriou
Nick Clifton
Richard Henderson
Eric Christopher
Andreas Jaeger
Thiemo Seufer
Frank Ch. Eigler
Ben Elliston
Geoffrey Keating
John Healy
Hans-Peter Nilsson
Kazu Hirata
Jan Hubicka
Patrick Macdonald
Jeff Johnston
Jakub Jelinek
Jim Wilson
H.J. Lu
Denis Chertykov
Dave Brolley
Donald Lindsay
J.T. Conklin
Andrew Haley
Gavin Koch
Michael Meissner
Diego Novillo
Ian Lance Taylor
Doug Evans