Commit Graph

82 Commits

Author SHA1 Message Date
Alan Modra 46b487005a update copyright dates 2009-09-02 07:21:40 +00:00
Doug Evans eea6c2c9c3 * i386.h: Add comment regarding sse* insns and prefixes. 2009-02-06 23:14:34 +00:00
Doug Evans 88db8cbb6a * opcode/i386.h: Add multiple inclusion protection.
(EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
	(EDI_REG_NUM): New macros.
	(MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
	(SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
	(REG_PREFIX_P): New macro.

	* amd64-tdep.h (amd64_displaced_step_copy_insn): Declare.
	(amd64_displaced_step_fixup): Declare.
	* amd64-tdep.c: #include opcode/i386.h, dis-asm.h.
	(amd64_arch_regmap): Move out of amd64_analyze_stack_align
	and make static global.
	(amd64_arch_regmap_len): New static global.
	(amd64_arch_reg_to_regnum): New function.
	(struct amd64_insn): New struct.
	(struct displaced_step_closure): New struct.
	(onebyte_has_modrm,twobyte_has_modrm): New static globals.
	(rex_prefix_p,skip_prefixes)
	(amd64_insn_length_fprintf,amd64_insn_length_init_dis)
	(amd64_insn_length,amd64_get_unused_input_int_reg)
	(amd64_get_insn_details,fixup_riprel,fixup_displaced_copy)
	(amd64_displaced_step_copy_insn)
	(amd64_absolute_jmp_p,amd64_absolute_call_p,amd64_ret_p)
	(amd64_call_p,amd64_breakpoint_p,amd64_syscall_p)
	(amd64_displaced_step_fixup): New functions.
	* amd64-linux-tdep.c: #include arch-utils.h.
	(amd64_linux_init_abi): Install displaced stepping support.

	* gdb.arch/amd64-disp-step.S: New file.
	* gdb.arch/amd64-disp-step.exp: New file.
	* gdb.arch/i386-disp-step.S: New file.
	* gdb.arch/i386-disp-step.exp: New file.
2009-01-29 00:29:53 +00:00
H.J. Lu f47b47fb18 binutils/
2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>

	* dwarf.c (dwarf_regnames_i386): Add AVX registers.
	(dwarf_regnames_x86_64): Likewise.

gas/

2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>

	* NEWS: Mention AES, CLMUL, AVX/FMA and -msse2avx.

	* doc/c-i386.texi: Add avx, aes, clmul and fma to -march=.
	Document -msse2avx, .avx, .aes, .clmul and .fma.

	* config/tc-i386.c (YMMWORD_MNEM_SUFFIX): New.
	(vex_prefix): Likewise.
	(sse2avx): Likewise.
	(CPU_FLAGS_ARCH_MATCH): Likewise.
	(CPU_FLAGS_64BIT_MATCH): Likewise.
	(CPU_FLAGS_32BIT_MATCH): Likewise.
	(CPU_FLAGS_PERFECT_MATCH): Likewise.
	(regymm): Likewise.
	(vex_imm4): Likewise.
	(fits_in_imm4): Likewise.
	(build_vex_prefix): Likewise.
	(VEX_check_operands): Likewise.
	(bad_implicit_operand): Likewise.
	(OPTION_MSSE2AVX): Likewise.
	(T_YMMWORD): Likewise.
	(_i386_insn): Add vex.
	(cpu_arch): Add .avx, .aes, .clmul and .fma.
	(cpu_flags_match): Changed to take a pointer to const template.
	Enable encoding SSE instructions with VEX prefix for -msse2avx.
	(match_mem_size): Also check ymmword.
	(operand_type_match): Clear ymmword.
	(md_begin): Allow '_' in mnemonic.
	(type_names): Add OPERAND_TYPE_VEX_IMM4.
	(process_immext): Update assert.
	(md_assemble): Don't call process_immext if sse2avx and immext
	are true.  Call build_vex_prefix if vex is true.
	(parse_insn): Updated for cpu_flags_match.
	(swap_operands): Handle 5 operands.
	(match_template): Handle 5 operands. Updated for cpu_flags_match.
	Check regymm.  Call VEX_check_operands. Handle YMMWORD_MNEM_SUFFIX.
	(process_suffix): Handle YMMWORD_MNEM_SUFFIX.
	(check_byte_reg): Check regymm.
	(process_operands): Duplicate the destination register for
	-msse2avx if needed.
	(build_modrm_byte): Updated for instructions with VEX encoding.
	(output_insn): Output VEX prefix if needed.
	(md_longopts): Add msse2avx.
	(md_parse_option): Handle OPTION_MSSE2AVX.
	(md_show_usage): Add avx, aes, clmul, fma and -msse2avx.
	(intel_e09): Support YMMWORD.
	(intel_e11): Likewise.
	(intel_get_token): Likewise.

gas/testsuite/

2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/i386/i386.exp: Run aes, aes-intel, x86-64-aes,
	x86-64-aes-intel, avx, avx-intel, inval-avx, x86-64-avx,
	x86-64-avx-intel and x86-64-inval-avx.

	* gas/cfi/cfi-i386.s: Add tests for AVX register maps.
	* gas/cfi/cfi-x86_64.s: Likewise.

	* gas/i386/aes.d: New.
	* gas/i386/aes.s: Likewise.
	* gas/i386/aes-intel.d: Likewise.
	* gas/i386/avx.d: Likewise.
	* gas/i386/avx.s: Likewise.
	* gas/i386/avx-intel.d: Likewise.
	* gas/i386/clmul.d: Likewise.
	* gas/i386/clmul-intel.d: Likewise.
	* gas/i386/clmul.s: Likewise.
	* gas/i386/i386.exp: Likewise.
	* gas/i386/inval-avx.l: Likewise.
	* gas/i386/inval-avx.s: Likewise.
	* gas/i386/sse2avx.d: Likewise.
	* gas/i386/sse2avx.s: Likewise.
	* gas/i386/x86-64-aes.d: Likewise.
	* gas/i386/x86-64-aes.s: Likewise.
	* gas/i386/x86-64-aes-intel.d: Likewise.
	* gas/i386/x86-64-avx.d: Likewise.
	* gas/i386/x86-64-avx.s: Likewise.
	* gas/i386/x86-64-avx-intel.d: Likewise.
	* gas/i386/x86-64-clmul.d: Likewise.
	* gas/i386/x86-64-clmul-intel.d: Likewise.
	* gas/i386/x86-64-clmul.s: Likewise.
	* gas/i386/x86-64-inval-avx.l: Likewise.
	* gas/i386/x86-64-inval-avx.s: Likewise.
	* gas/i386/x86-64-sse2avx.d: Likewise.
	* gas/i386/x86-64-sse2avx.s: Likewise.

	* gas/i386/arch-10.s: Add tests for AVX, AES, CLMUL and FMA.
	* gas/i386/x86-64-arch-2.s: Likewise.

	* gas/i386/rexw.s: Add AVX tests.

	* gas/i386/x86-64-opcode-inval.s: Remove lds/les test.

	* gas/cfi/cfi-i386.d: Updated.
	* gas/cfi/cfi-x86_64.d: Likewise.
	* gas/i386/arch-10.d:  Likewise.
	* gas/i386/arch-10-1.l: Likewise.
	* gas/i386/arch-10-2.l: Likewise.
	* gas/i386/arch-10-3.l: Likewise.
	* gas/i386/arch-10-4.l: Likewise.
	* gas/i386/rexw.d: Likewise.
	* gas/i386/x86-64-arch-2.d: Likewise.
	* gas/i386/x86-64-opcode-inval.d: Likewise.
	* gas/i386/x86-64-opcode-inval-intel.d: Likewise.

include/opcode/

2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>

	* i386.h (MAX_OPERANDS): Set to 5.
	(MAX_MNEM_SIZE): Changed to 20.

opcodes/

2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (OP_E_register): New.
	(OP_E_memory): Likewise.
	(OP_VEX): Likewise.
	(OP_EX_Vex): Likewise.
	(OP_EX_VexW): Likewise.
	(OP_XMM_Vex): Likewise.
	(OP_XMM_VexW): Likewise.
	(OP_REG_VexI4): Likewise.
	(PCLMUL_Fixup): Likewise.
	(VEXI4_Fixup): Likewise.
	(VZERO_Fixup): Likewise.
	(VCMP_Fixup): Likewise.
	(VPERMIL2_Fixup): Likewise.
	(rex_original): Likewise.
	(rex_ignored): Likewise.
	(Mxmm): Likewise.
	(XMM): Likewise.
	(EXxmm): Likewise.
	(EXxmmq): Likewise.
	(EXymmq): Likewise.
	(Vex): Likewise.
	(Vex128): Likewise.
	(Vex256): Likewise.
	(VexI4): Likewise.
	(EXdVex): Likewise.
	(EXqVex): Likewise.
	(EXVexW): Likewise.
	(EXdVexW): Likewise.
	(EXqVexW): Likewise.
	(XMVex): Likewise.
	(XMVexW): Likewise.
	(XMVexI4): Likewise.
	(PCLMUL): Likewise.
	(VZERO): Likewise.
	(VCMP): Likewise.
	(VPERMIL2): Likewise.
	(xmm_mode): Likewise.
	(xmmq_mode): Likewise.
	(ymmq_mode): Likewise.
	(vex_mode): Likewise.
	(vex128_mode): Likewise.
	(vex256_mode): Likewise.
	(USE_VEX_C4_TABLE): Likewise.
	(USE_VEX_C5_TABLE): Likewise.
	(USE_VEX_LEN_TABLE): Likewise.
	(VEX_C4_TABLE): Likewise.
	(VEX_C5_TABLE): Likewise.
	(VEX_LEN_TABLE): Likewise.
	(REG_VEX_XX): Likewise.
	(MOD_VEX_XXX): Likewise.
	(PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
	(PREFIX_0F3A44): Likewise.
	(PREFIX_0F3ADF): Likewise.
	(PREFIX_VEX_XXX): Likewise.
	(VEX_OF): Likewise.
	(VEX_OF38): Likewise.
	(VEX_OF3A): Likewise.
	(VEX_LEN_XXX): Likewise.
	(vex): Likewise.
	(need_vex): Likewise.
	(need_vex_reg): Likewise.
	(vex_i4_done): Likewise.
	(vex_table): Likewise.
	(vex_len_table): Likewise.
	(OP_REG_VexI4): Likewise.
	(vex_cmp_op): Likewise.
	(pclmul_op): Likewise.
	(vpermil2_op): Likewise.
	(m_mode): Updated.
	(es_reg): Likewise.
	(PREFIX_0F38F0): Likewise.
	(PREFIX_0F3A60): Likewise.
	(reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
	(prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
	and PREFIX_VEX_XXX entries.
	(x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
	(three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
	PREFIX_0F3ADF.
	(mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
	Add MOD_VEX_XXX entries.
	(ckprefix): Initialize rex_original and rex_ignored.  Store the
	REX byte in rex_original.
	(get_valid_dis386): Handle the implicit prefix in VEX prefix
	bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
	(print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
	calling get_valid_dis386.  Use rex_original and rex_ignored when
	printing out REX.
	(putop): Handle "XY".
	(intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
	ymmq_mode.
	(OP_E_extended): Updated to use OP_E_register and
	OP_E_memory.
	(OP_XMM): Handle VEX.
	(OP_EX): Likewise.
	(XMM_Fixup): Likewise.
	(CMP_Fixup): Use ARRAY_SIZE.

	* i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
	CPU_FMA_FLAGS and CPU_AVX_FLAGS.
	(operand_type_init): Add OPERAND_TYPE_REGYMM and
	OPERAND_TYPE_VEX_IMM4.
	(cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
	(opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
	VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
	VexImmExt and SSE2AVX.
	(operand_types): Add RegYMM, Ymmword and Vex_Imm4.

	* i386-opc.h (CpuAVX): New.
	(CpuAES): Likewise.
	(CpuCLMUL): Likewise.
	(CpuFMA): Likewise.
	(Vex): Likewise.
	(Vex256): Likewise.
	(VexNDS): Likewise.
	(VexNDD): Likewise.
	(VexW0): Likewise.
	(VexW1): Likewise.
	(Vex0F): Likewise.
	(Vex0F38): Likewise.
	(Vex0F3A): Likewise.
	(Vex3Sources): Likewise.
	(VexImmExt): Likewise.
	(SSE2AVX): Likewise.
	(RegYMM): Likewise.
	(Ymmword): Likewise.
	(Vex_Imm4): Likewise.
	(Implicit1stXmm0): Likewise.
	(CpuXsave): Updated.
	(CpuLM): Likewise.
	(ByteOkIntel): Likewise.
	(OldGcc): Likewise.
	(Control): Likewise.
	(Unspecified): Likewise.
	(OTMax): Likewise.
	(i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
	(i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
	vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
	vex3sources, veximmext and sse2avx.
	(i386_operand_type): Add regymm, ymmword and vex_imm4.

	* i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.

	* i386-reg.tbl: Add AVX registers, ymm0..ymm15.

	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
2008-04-03 14:03:20 +00:00
H.J. Lu 3ce0c60b4c gas/
2003-03-21  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.c: Replace REX_MODE64, REX_EXTX, REX_EXTY
	and REX_EXTZ with REX_W, REX_R, REX_X and REX_B respectively.

include/opcode/

2003-03-21  H.J. Lu  <hongjiu.lu@intel.com>

	* i386.h (REX_MODE64): Renamed to ...
	(REX_W): This.
	(REX_EXTX): Renamed to ...
	(REX_R): This.
	(REX_EXTY): Renamed to ...
	(REX_X): This.
	(REX_EXTZ): Renamed to ...
	(REX_B): This.

opcodes/

2003-03-21  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (REX_MODE64): Remove definition.
	(REX_EXTX): Likewise.
	(REX_EXTY): Likewise.
	(REX_EXTZ): Likewise.
	(USED_REX): Use REX_OPCODE instead of 0x40.
	Replace REX_MODE64, REX_EXTX, REX_EXTY and REX_EXTZ with REX_W,
	REX_R, REX_X and REX_B respectively.
2007-03-21 21:23:43 +00:00
H.J. Lu e96d068ed3 gas/
2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>

	* Makefile.am: Run "make dep-am".
	* Makefile.in: Regenerated.

	* config/tc-i386.c: Include "opcodes/i386-opc.h" instead of
	"opcode/i386.h".
	(md_begin): Check reg_name != NULL for the last entry in
	i386_regtab.

	* config/tc-i386.h: Move many entries to opcode/i386.h and
	opcodes/i386-opc.h.

	* configure.in (need_opcodes): Set true for i386.
	* configure: Regenerated.

include/opcode/

2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>

	* i386.h: Add entries from config/tc-i386.h and move tables
	to opcodes/i386-opc.h.

opcodes/

2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>

	* Makefile.am (CFILES): Add i386-opc.c.
	(ALL_MACHINES): Add i386-opc.lo.
	Run "make dep-am".
	* Makefile.in: Regenerated.

	* configure.in: Add i386-opc.lo for bfd_i386_arch.
	* configure: Regenerated.

	* i386-dis.c: Include "opcode/i386.h".
	(MAXLEN): Renamed to MAX_MNEM_SIZE. Remove definition.
	(FWAIT_OPCODE): Remove definition.
	(UNIXWARE_COMPAT): Renamed to SYSV386_COMPAT. Remove definition.
	(MAX_OPERANDS): Remove definition.

	* i386-opc.c: New file.
	* i386-opc.h: Likewise.
2007-03-15 14:31:24 +00:00
H.J. Lu d7e13a06c2 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
* i386.h (FloatDR): Removed.
	(i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
2007-03-14 03:26:06 +00:00
Alan Modra 77da924b40 gas/
* config/tc-i386.h (Seg2ShortForm, Seg3ShortForm): Delete.
	* config/tc-i386.c: Wrap overly long lines, whitespace fixes.
	(process_operands): Move old Seg2ShortForm and Seg3ShortForm
	code, and test for these insns using a combination of
	opcode_modifier and operand_types.
include/opcode/
	* i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
	and Seg3ShortFrom with Shortform.
2007-02-13 23:23:53 +00:00
H.J. Lu 79010c3b34 gas/testsuite/
2007-02-11  H.J. Lu  <hongjiu.lu@intel.com>

	PR gas/4027
	* gas/i386/opcode.s: Add more tests for "test".
	* i386/opcode-intel.d: Updated.
	* gas/i386/opcode-suffix.d: Likewise.
	* gas/i386/opcode.d: Likewise.

include/opcode/

2007-02-11  H.J. Lu  <hongjiu.lu@intel.com>

	PR gas/4027
	* i386.h (i386_optab): Put the real "test" before the pseudo
	one.
2007-02-12 04:51:40 +00:00
H.J. Lu baf35b5d76 gas/
2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.h (CpuPNI): Removed.
	(CpuUnknownFlags): Replace CpuPNI with CpuSSE3.
	* config/tc-i386.c (md_assemble): Likewise.

include/opcode/

2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>

	* i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
2006-11-08 19:56:02 +00:00
Michael Meissner 7e39651a54 Fix AMDFAM10 POPCNT instruction 2006-10-23 22:53:28 +00:00
H.J. Lu 5c9dda86e5 gas/
2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.h (CpuMNI): Renamed to ...
	(CpuSSSE3): This.
	(CpuUnknownFlags): Updated.
	(processor_type): Replace PROCESSOR_YONAH with PROCESSOR_CORE
	and PROCESSOR_MEROM with PROCESSOR_CORE2.
	* config/tc-i386.c: Updated.
	* doc/c-i386.texi: Likewise.

	* config/tc-i386.c (cpu_arch): Add ".ssse3", "core" and "core2".

include/opcode/

2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>

	* i386.h: Replace CpuMNI with CpuSSSE3.
2006-09-28 14:06:36 +00:00
H.J. Lu 62f94a893e 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
* i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
	movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
	movdq2q and movq2dq.
2006-07-14 16:15:27 +00:00
Michael Meissner 2d73611e56 Add amdfam10 instructions 2006-07-13 22:25:48 +00:00
H.J. Lu acfd62fdfa gas/testsuite/
2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/i386/i386.exp: Run nops and x86-64-nops.

	* gas/i386/nops.d: New file.
	* gas/i386/nops.s: Likewise.
	* gas/i386/x86-64-nops.d: Likewise.
	* gas/i386/x86-64-nops.s: Likewise.

include/opcode/

2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>

	* i386.h (i386_optab): Add "nop" with memory reference.

opcodes/

2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (dis386_twobyte): Use "nopQ" for 0x1f.
	(twobyte_has_modrm): Set 1 for 0x1f.
2006-06-12 18:59:36 +00:00
H.J. Lu 2d853d0e39 gas/
2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.c (process_suffix): Don't add rex64 for
	"xchg %rax,%rax".

gas/testsuite/

2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/i386/opcode.s: Add "xchg %ax,%ax".
	* gas/i386/opcode.d: Updated.

	* gas/i386/x86-64-opcode.s: Add xchg %ax,%ax, xchg %eax,%eax,
	xchg %rax,%rax, rex64 xchg %rax,%rax and xchg %rax,%r8.
	* gas/i386/x86-64-opcode.d: Updated.

include/opcode/

2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>

	* i386.h (i386_optab): Update comment for 64bit NOP.

opcodes/

2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (NOP_Fixup): Removed.
	(NOP_Fixup1): New.
	(NOP_Fixup2): Likewise.
	(dis386): Use NOP_Fixup1 and NOP_Fixup2 on 0x90.
2006-06-12 18:55:42 +00:00
H.J. Lu e3ff04608e gas/
2006-02-27  H.J. Lu <hongjiu.lu@intel.com>

	* gas/config/tc-i386.c (output_insn): Support Intel Merom New
	Instructions.

	* gas/config/tc-i386.h (CpuMNI): New.
	(CpuUnknownFlags): Add CpuMNI.

gas/testsuite/

2006-02-27  H.J. Lu <hongjiu.lu@intel.com>

	* gas/i386/i386.exp: Add merom and x86-64-merom.

	* gas/i386/merom.d: New file.
	* gas/i386/merom.s: Likewise.
	* gas/i386/x86-64-merom.d: Likewise.
	* gas/i386/x86-64-merom.s: Likewise.

include/opcode/

2006-02-27  H.J. Lu <hongjiu.lu@intel.com>

	* i386.h (i386_optab): Support Intel Merom New Instructions.

opcodes/

2006-02-27  H.J. Lu <hongjiu.lu@intel.com>

	* i386-dis.c (IS_3BYTE_OPCODE): New for 3-byte opcodes used by
	Intel Merom New Instructions.
	(THREE_BYTE_0): Likewise.
	(THREE_BYTE_1): Likewise.
	(three_byte_table): Likewise.
	(dis386_twobyte): Use THREE_BYTE_0 for entry 0x38. Use
	THREE_BYTE_1 for entry 0x3a.
	(twobyte_has_modrm): Updated.
	(twobyte_uses_SSE_prefix): Likewise.
	(print_insn): Handle 3-byte opcodes used by Intel Merom New
	Instructions.
2006-02-27 15:35:37 +00:00
H.J. Lu 466fc394b8 gas/
2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>

	PR gas/1874
	* config/tc-i386.c (match_template): Handle monitor.
	(process_suffix): Likewise.

gas/testsuite/

2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>

	PR gas/1874
	* gas/i386/i386.exp: Add x86-64-prescott for 64bit.

	* gas/i386/prescott.s: Test address size override for monitor.
	* gas/i386/prescott.d: Updated.

	* gas/i386/x86-64-prescott.d: New file.
	* gas/i386/x86-64-prescott.s: Likewise.

include/opcode/

2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>

	PR gas/1874
	* i386.h (i386_optab): Add 64bit support for monitor and mwait.

opcodes/

2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>

	PR gas/1874
	* i386-dis.c (address_mode): New enum type.
	(address_mode): New variable.
	(mode_64bit): Removed.
	(ckprefix): Updated to check address_mode instead of mode_64bit.
	(prefix_name): Likewise.
	(print_insn): Likewise.
	(putop): Likewise.
	(print_operand_value): Likewise.
	(intel_operand_size): Likewise.
	(OP_E): Likewise.
	(OP_G): Likewise.
	(set_op): Likewise.
	(OP_REG): Likewise.
	(OP_I): Likewise.
	(OP_I64): Likewise.
	(OP_OFF): Likewise.
	(OP_OFF64): Likewise.
	(ptr_reg): Likewise.
	(OP_C): Likewise.
	(SVME_Fixup): Likewise.
	(print_insn): Set address_mode.
	(PNI_Fixup): Add 64bit and address size override support for
	monitor and mwait.
2005-12-06 12:40:57 +00:00
Jan Beulich d08916dade include/opcode/
2005-07-27  Jan Beulich  <jbeulich@novell.com>

	* i386.h (i386_optab): Add comment to movd. Use LongMem for all
	movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
	Add movq-s as 64-bit variants of movd-s.
2005-07-27 07:04:31 +00:00
Jan Beulich 9d219da08a include/opcode/
2005-07-18  Jan Beulich  <jbeulich@novell.com>

	* i386.h (i386_optab): Operands of aam and aad are unsigned.
2005-07-18 06:11:00 +00:00
H.J. Lu f6cab85f3a gas/
2007-07-15  H.J. Lu <hongjiu.lu@intel.com>

	* gas/config/tc-i386.h (CpuVMX): New.
	(CpuUnknownFlags): Add CpuVMX.

gas/testsuite/

2007-07-15  H.J. Lu <hongjiu.lu@intel.com>

	* gas/i386/i386.exp: Add vmx and x86-64-vmx.

	* gas/i386/vmx.d: New file.
	* gas/i386/vmx.s: Likewise.
	* gas/i386/x86-64-vmx.d: Likewise.
	* gas/i386/x86-64-vmx.s: Likewise.

include/opcode/

2007-07-15  H.J. Lu <hongjiu.lu@intel.com>

	* i386.h (i386_optab): Support Intel VMX Instructions.

opcodes/

2007-07-15  H.J. Lu <hongjiu.lu@intel.com>

	* i386-dis.c (OP_VMX): New. Handle Intel VMX Instructions.
	(VMX_Fixup): New. Fix up Intel VMX Instructions.
	(Em): New.
	(Gm): New.
	(VM): New.
	(dis386_twobyte): Updated entries 0x78 and 0x79.
	(twobyte_has_modrm): Likewise.
	(grps): Use OP_VMX in the "sgdtIQ" entry. Updated GRP9.
	(OP_G): Handle m_mode.
2005-07-15 13:49:53 +00:00
Jan Beulich 35e456b7f5 gas/
2005-07-05  Jan Beulich  <jbeulich@novell.com>

	* config/tc-i386.h (CpuSVME): New.
	(CpuUnknownFlags): Include CpuSVME.
	* config/tc-i386.c (cpu_arch): Add .pacifica and .svme. Add opteron
	as alias of sledgehammer.
	(md_assemble): Include invlpga in the check for insns with two source
	operands.
	(process_operands): Include SVME insns in the check for ignored
	segment overrides. Adjust diagnostic.
	(i386_index_check): Special-case SVME insns with memory operands.

gas/testsuite/
2005-07-05  Jan Beulich  <jbeulich@novell.com>

	* gas/i386/svme.d: New.
	* gas/i386/svme.s: New.
	* gas/i386/svme64.d: New.
	* gas/i386/i386.exp: Run new tests.

include/opcode/
2005-07-05  Jan Beulich  <jbeulich@novell.com>

	* i386.h (i386_optab): Add new insns.

opcodes/
2005-07-05  Jan Beulich  <jbeulich@novell.com>

	* i386-dis.c (SVME_Fixup): New.
	(grps): Use it for the lidt entry.
	(PNI_Fixup): Call OP_M rather than OP_E.
	(INVLPG_Fixup): Likewise.
2005-07-05 07:16:53 +00:00
H.J. Lu 1d74c8ce77 gas/
2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>

	PR 1013
	* config/tc-i386.c (md_assemble): Don't call optimize_disp on
	movabs.
	(optimize_disp): Optimize only if possible. Don't use 64bit
	displacement on non-constants and do same on constants if
	possible.

gas/testsuite/

2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>

	PR 1013
	* i386/x86_64.s: Add absolute 64bit addressing tests for mov.
	* i386/x86_64.s: Updated.

include/opcode/

2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>

	PR 1013
	* i386.h (i386_optab): Update comments for 64bit addressing on
	mov. Allow 64bit addressing for mov and movq.
2005-06-20 23:18:38 +00:00
Nick Clifton d699bc988f Update the address and phone number of the FSF organization 2005-05-10 10:21:13 +00:00
Jan Beulich b6487cdedb gas/
2005-05-09  Jan Beulich  <jbeulich@novell.com>

	* config/tc-i386.c (parse_insn): Disallow use of prefix separator
	and comma in Intel mode.

include/opcode/
2005-05-09  Jan Beulich  <jbeulich@novell.com>

	* i386.h (i386_optab): Add ht and hnt.
2005-05-09 06:49:01 +00:00
Mark Kettenis 3b4ed14c7c gas/ChangeLog:
* config/tc-i386.c (md_begin): Allow hyphens in mnemonics.
include/opcode/ChangeLog:
* i386.h: Insert hyphens into selected VIA PadLock extensions.
Add xcrypt-ctr.  Provide aliases without hyphens.
opcodes/ChangeLog:
* i386-dis.c: Insert hyphens into selected VIA PadLock extensions.
Add xcrypt-ctr.
2005-04-18 20:59:19 +00:00
Mark Kettenis 48c2393632 include/opcode/ChangeLog:
* i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
adjust them accordingly.
gas/ChangeLog:
* config/tc-i386.c (output_insn): Handle VIA PadLock instructions
similar to other instructions now that they're marked as ImmExt.
2005-04-12 17:12:30 +00:00
Jan Beulich 46390451a4 include/opcode/
2005-04-01  Jan Beulich  <jbeulich@novell.com>

	* i386.h (i386_optab): Add rdtscp.

opcodes/
2005-04-01  Jan Beulich  <jbeulich@novell.com>

	* i386-dis.c (INVLPG_Fixup): Decode rdtscp; change code to allow for
	easier future additions.
2005-04-01 16:03:39 +00:00
H.J. Lu ed874f87e0 gas/testsuite/
2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/i386/i386.exp: Run segment and inval-seg for i386. Run
	x86-64-segment and x86-64-inval-seg for x86-64.

	* gas/i386/intel.d: Expect movw for moving between memory and
	segment register.
	* gas/i386/naked.d: Likewise.
	* gas/i386/opcode.d: Likewise.
	* gas/i386/x86-64-opcode.d: Likewise.

	* gas/i386/opcode.s: Use movw for moving between memory and
	segment register.
	* gas/i386/x86-64-opcode.s: Likewise.

	* : Likewise.

	* gas/i386/inval-seg.l: New.
	* gas/i386/inval-seg.s: New.
	* gas/i386/segment.l: New.
	* gas/i386/segment.s: New.
	* gas/i386/x86-64-inval-seg.l: New.
	* gas/i386/x86-64-inval-seg.s: New.
	* gas/i386/x86-64-segment.l: New.
	* gas/i386/x86-64-segment.s: New.

include/opcode/

2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>

	* i386.h (i386_optab): Don't allow the `l' suffix for moving
	moving between memory and segment register. Allow movq for
	moving between general-purpose register and segment register.

opcodes/

2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (SEG_Fixup): New.
	(Sv): New.
	(dis386): Use "Sv" for 0x8c and 0x8e.
2005-03-29 19:30:46 +00:00
Alan Modra 3aeffaadc7 update copyright dates 2005-03-03 11:58:10 +00:00
Jan Beulich b51b23bf82 gas/testsuite/
2005-02-09  Jan Beulich  <jbeulich@novell.com>

	* gas/i386/intelok.s: Remove comments disabling alternative forms of
	fbld, fbstp, and fldcw.
	* gas/i386/intelok.d: Expect two instances of fbld, fbstp, and fldcw.

include/opcode/
2005-02-09  Jan Beulich  <jbeulich@novell.com>

	PR gas/707
	* i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
	FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
	fnstsw.
2005-02-09 08:05:43 +00:00
Jan Beulich c1ab3396dc gas/
2004-11-25 Jan Beulich <jbeulich@novell.com>

	* config/tc-i386.c (optimize_imm): Adjust immediates to only those
	permissible for the selected instruction suffix.
	(process_suffix): For DefaultSize instructions, suppressing the
	guessing of a 'q' suffix if the instruction doesn't support it is
	pointless, because only an 'l' suffix can be guessed in this place.

gas/testsuite/
2004-11-25 Jan Beulich <jbeulich@novell.com>
	* gas/i386/x86-64-inval.[sl]: Remove sahf/lahf.

include/opcode/
2004-11-25 Jan Beulich <jbeulich@novell.com>

	* i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
	to/from test registers are illegal in 64-bit mode. Add missing
	NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
	(previously one had to explicitly encode a rex64 prefix). Re-enable
	lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
	support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
2004-11-25 08:42:54 +00:00
Jan Beulich 4b8e88e31d gas/
2004-11-23 Jan Beulich <jbeulich@novell.com>

	* config/tc-i386.h (CpuMMX2): Declare. Artificial classifier to
	indicate the MMX extensions added by both SSE and 3DNow!A.
	(Cpu3dnowA): Declare.
	(CpuUnknownFlags): Update.
	* config/tc-i386.c (cpu_sub_arch_name): Declare.
	(cpu_arch): i586 and pentium do not imply MMX. i686 and pentiumpro do
	neither imply SSE nor MMX. k6 implies MMX. k6_2 additionally implies
	3DNow!. Athlon additionally implies 3DNow!A. Several new
	entries (those starting with a dot are for sub-arch specification).
	(set_cpu_arch): Handle sub-arch specifications.
	(parse_insn): Distinguish between instructions not supported because
	of insufficient CPU features and because of 64-bit mode.
	* doc/c-i386.texi: Describe enhanced .arch directive.

include/opcode/
2004-11-23 Jan Beulich <jbeulich@novell.com>

	* i386.h (i386_optab): paddq and psubq, even in their MMX form, are
	available only with SSE2. Change the MMX additions introduced by SSE
	and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
	instructions by their now designated identifier (since combining i686
	and 3DNow! does not really imply 3DNow!A).
2004-11-23 07:55:12 +00:00
H.J. Lu d356aef3c4 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
* i386.h (i386_optab): Put back "movzb".
2004-11-05 23:14:30 +00:00
Jan Beulich 1fede1b1ba gas/
2004-11-04 Jan Beulich <jbeulich@novell.com>

	* config/tc-i386.c (set_intel_syntax): Allow % in symbol names when
	intel syntax and no register prefix, allow $ in symbol names when
	intel syntax.
	(set_16bit_gcc_code_flag): Replace literal 'l' by LONG_MNEM_SUFFIX.
	(intel_float_operand): Add fourth return value indicating math control
	operations. Make classification more precise.
	(md_assemble): Complain if memory operand of mov[sz]x has no size
	specified.
	(parse_insn): Translate word operands to floating point instructions
	operating on integers as well as control instructions to short ones
	as expected by AT&T syntax. Translate 'd' suffix to short one only for
	floating point instructions operating on non-integer operands.
	(match_template): Remove fldcw special case. Adjust q-suffix handling
	to permit it on fild/fistp/fisttp in AT&T mode.
	(process_suffix): Don't guess DefaultSize insns' suffix from
	stackop_size for certain floating point control instructions. Guess
	suffix for branch and [ls][gi]dt based on flag_code. Split error
	messages for Intel and AT&T syntax, and make the condition more strict
	for the former. Adjust suppressing of generation of operand size
	overrides.
	(intel parser): Allow the full set of MASM operators. Add FWORD, TBYTE,
	OWORD, and XMMWORD operand size specifiers (TBYTE replaces XWORD). Add
	more error checking.
	* config/tc-i386.h (BYTE_PTR WORD_PTR DWORD_PTR QWORD_PTR XWORD_PTR
	SHORT OFFSET_FLAT FLAT NONE_FOUND): Remove unused defines.

gas/testsuite/
2004-11-04 Jan Beulich <jbeulich@novell.com>
	* gas/i386/i386.exp: Execute new tests intelbad and intelok.
	* gas/i386/intelbad.[sl]: New test to check for various things not
	permitted in Intel mode.
	* gas/i386/intel.d, gas/i386/opcode.d, gas/i386/x86-64-opcode.d:
	Adjust for change to segment register store.
	* gas/i386/intelok.[sd]: New test to check various Intel mode specific
	things get handled correctly.
	* gas/i386/x86_64.[sd]: Remove unsupported constructs referring to
	'high' and 'low' parts of an operand, which the parser previously
	accepted while neither telling that it's not supported nor that it
	ignored the remainder of the line following these supposed keywords.

include/opcode/
2004-11-04 Jan Beulich <jbeulich@novell.com>

	* i386.h (sldx_Suf): Remove.
	(FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
	(q_FP): Define, implying no REX64.
	(x_FP, sl_FP): Imply FloatMF.
	(i386_optab): Split reg and mem forms of moving from segment registers
	so that the memory forms can ignore the 16-/32-bit operand size
	distinction. Adjust a few others for Intel mode. Remove *FP uses from
	all non-floating-point instructions. Unite 32- and 64-bit forms of
	movsx, movzx, and movd. Adjust floating point operations for the above
	changes to the *FP macros. Add DefaultSize to floating point control
	insns operating on larger memory ranges. Remove left over comments
	hinting at certain insns being Intel-syntax ones where the ones
	actually meant are already gone.

opcodes/
2004-11-04 Jan Beulich <jbeulich@novell.com>

	* i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define.
	(indirEb): Remove.
	(Mp): Use f_mode rather than none at all.
	(t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode
	replaces what previously was x_mode; x_mode now means 128-bit SSE
	operands.
	(dis386): Make far jumps and calls have an 'l' prefix only in AT&T
	mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq.
	pinsrw's second operand is Edqw.
	(grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's
	operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt,
	fldenv, frstor, fsave, fstenv all should also have suffixes in Intel
	mode when an operand size override is present or always suffixing.
	More instructions will need to be added to this group.
	(putop): Handle new macro chars 'C' (short/long suffix selector),
	'I' (Intel mode override for following macro char), and 'J' (for
	adding the 'l' prefix to far branches in AT&T mode). When an
	alternative was specified in the template, honor macro character when
	specified for Intel mode.
	(OP_E): Handle new *_mode values. Correct pointer specifications for
	memory operands. Consolidate output of index register.
	(OP_G): Handle new *_mode values.
	(OP_I): Handle const_1_mode.
	(OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate
	respective opcode prefix bits have been consumed.
	(OP_EM, OP_EX): Provide some default handling for generating pointer
	specifications.
2004-11-04 09:16:08 +00:00
Michal Ludvig f048a4a16f Added new instructions for next version of VIA PadLock core. 2004-07-30 12:36:37 +00:00
H.J. Lu 7b313f6fc8 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
* i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
2004-07-22 19:10:49 +00:00
Nick Clifton 9aec2c3c19 For DefaultSize instructions, don't guess a 'q' suffix if the instruction
doesn't support it.
2004-07-21 18:18:04 +00:00
Alan Modra 98767b49a0 include/opcode/
* i386.h (i386_optab): Remove fildd, fistpd and fisttpd.

opcodes/
	* i386-dis.c (x_mode): Comment.
	(two_source_ops): File scope.
	(float_mem): Correct fisttpll and fistpll.
	(float_mem_mode): New table.
	(dofloat): Use it.
	(OP_E): Correct intel mode PTR output.
	(ptr_reg): Use open_char and close_char.
	(PNI_Fixup): Handle possible suffix on sidt.  Use op1out etc. for
	operands.  Set two_source_ops.

gas/testsuite/
	* gas/i386/prescott.s: Remove fisttpd and fisttpq.
	* gas/i386/prescott.d: Update.
2004-06-23 15:06:53 +00:00
Michal Ludvig cbc2ab7c83 2004-03-12 Michal Ludvig <mludvig@suse.cz>
* i386.h (i386_optab): Added xstore as an alias for xstorerng.
2004-03-12 13:38:46 +00:00
Jakub Jelinek 1260d0e446 * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
(INVLPG_Fixup): New function.
	(PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.

	* opcode/i386.h (i386_optab): Remove CpuNo64 from sysenter and
	sysexit.
2004-03-12 10:47:49 +00:00
Michal Ludvig 75f1011bbf 2004-03-12 Michal Ludvig <mludvig@suse.cz>
* gas/config/tc-i386.c (output_insn): Handle PadLock instructions.
	* gas/config/tc-i386.h (CpuPadLock): New define.
	(CpuUnknownFlags): Added CpuPadLock.
	* include/opcode/i386.h (i386_optab): Added xstore/xcrypt insns.
	* opcodes/i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
	(dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
	(padlock_table): New struct with PadLock instructions.
	(print_insn): Handle PADLOCK_SPECIAL.
2004-03-12 10:14:29 +00:00
H.J. Lu 203515ee13 gas/
2003-06-23  H.J. Lu <hongjiu.lu@intel.com>

	* gas/config/tc-i386.c (md_assemble): Support Intel Precott New
	Instructions.

	* gas/config/tc-i386.h (CpuPNI): New.
	(CpuUnknownFlags): Add CpuPNI.

gas/testsuite/

2003-06-23  H.J. Lu <hongjiu.lu@intel.com>

	* gas/i386/i386.exp: Add prescott.

	* gas/i386/prescott.d: New file.
	* gas/i386/prescott.s: Likewise.

include/opcode/

2003-06-23  H.J. Lu <hongjiu.lu@intel.com>

	* i386.h (i386_optab): Support Intel Precott New Instructions.

opcodes/

2003-06-23  H.J. Lu <hongjiu.lu@intel.com>

	* i386-dis.c (PNI_Fixup): New. Fix up "mwait" and "monitor" in
	Intel Precott New Instructions.
	(PREGRP27): New. Added for "addsubpd" and "addsubps".
	(PREGRP28): New. Added for "haddpd" and "haddps".
	(PREGRP29): New. Added for "hsubpd" and "hsubps".
	(PREGRP30): New. Added for "movsldup" and "movddup".
	(PREGRP31): New. Added for "movshdup" and "movhpd".
	(PREGRP32): New. Added for "lddqu".
	(dis386_twobyte): Use PREGRP30 to replace the "movlpX" entry.
	Use PREGRP31 to replace the "movhpX" entry. Use PREGRP28 for
	entry 0x7c. Use PREGRP29 for entry 0x7d. Use PREGRP27 for
	entry 0xd0. Use PREGRP32 for entry 0xf0.
	(twobyte_has_modrm): Updated.
	(twobyte_uses_SSE_prefix): Likewise.
	(grps): Use PNI_Fixup in the "sidtQ" entry.
	(prefix_user_table): Add PREGRP27, PREGRP28, PREGRP29, PREGRP30,
	PREGRP31 and PREGRP32.
	(float_mem): Use "fisttp{l||l|}" in entry 1 in opcode 0xdb.
	Use "fisttpll" in entry 1 in opcode 0xdd.
	Use "fisttp" in entry 1 in opcode 0xdf.
2003-06-23 20:15:33 +00:00
Alan Modra 23c3a85872 gas/ChangeLog
* config/tc-i386.c (process_suffix): Remove intel mode movsx and
	movzx fudges.
	(md_assemble): Instead, zap the suffix here.

include/opcode/ChangeLog
	* i386.h: Remove IgnoreSize from movsx and movzx.
2002-07-08 10:03:11 +00:00
Alan Modra d6e14e29f1 reorder cmpsd, movsd 2002-04-11 11:58:30 +00:00
Alan Modra 9ddd9fb225 * i386.h: Add intel mode cmpsd and movsd. 2002-04-11 10:21:58 +00:00
Jan Hubicka dda54ada03 * i386.h (push,pop): Fix Reg64 to WordReg to allow 16bit operands. 2002-02-18 16:32:25 +00:00
Jan Hubicka 2b14b2d6da * i386.h (push,pop): Allow 16bit operands in 64bit mode.
(xchg): Fix.
	(in, out): Disable 64bit operands.
	(call, jmp): Avoid REX prefixes.
	(jcxz): Prohibit in 64bit mode
	(jrcxz, loop): Add 64bit variants.
	(movq): Fix patterns.
	(movmskps, pextrw, pinstrw): Add 64bit variants.
2002-02-11 11:56:20 +00:00
Alan Modra f513298e18 * i386.h (i386_optab): Add entries for "sldr", "smsw" and "str" to
accept WordReg.
	* i386-dis.c (grps): Change "sldt", "str", and "smsw" entries
	to "sldtQ", "strQ", "smswQ" respectively; all with Ev operand
	category instead of Ew.
2001-11-13 01:03:55 +00:00
Alan Modra 24a474a4aa Correct cvtps2dq, movdq2q, movq2dq, and movq problems. 2001-05-12 09:52:39 +00:00