libs/newlib-cygwin
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newlib-cygwin
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5 Commits

Author SHA1 Message Date
Keith Packard 5377a84776 riscv: Map between ieeefp.h exception bits and RISC-V FCSR bits 
If we had architecture-specific exception bits, we could just set them
to match the processor, but instead ieeefp.h is shared by all targets
so we need to map between the public values and the register contents.

Signed-off-by: Keith Packard <keithp@keithp.com>
 2020-01-21 10:28:35 +01:00
Keith Packard 8e74c7119f riscv: Add 'break' statements to fpsetround switch 
This makes the fpsetround function actually do something rather than
just return -1 due to the default 'fall-through' behavior of the switch
statement.

Signed-off-by: Keith Packard <keithp@keithp.com>
 2020-01-21 10:28:35 +01:00
Keith Packard 954504ea14 riscv: Use current pseudo-instructions to access the FCSR register 
Use fscsr and frcsr to store and read the FCSR register instead of
fssr and frsr.

Signed-off-by: Keith Packard <keithp@keithp.com>
 2020-01-21 10:28:35 +01:00
Kito Cheng 6864c08b94 Change license to FreeBSD License for RISC-V 
- For prevent confuse about what BSD license variant we used, 2- or
   3-clause license, we change the license to FreeBSD license to make
   it unambiguously refers to the 2-clause license.
 2017-08-21 11:08:54 +02:00
Kito Cheng 363dbb9e44 Add RISC-V port for newlib 
Contributor list:
    - Andrew Waterman  <andrew@sifive.com>
    - Palmer Dabbelt  <palmer@dabbelt.com>
    - Kito Cheng  <kito.cheng@gmail.com>
    - Scott Beamer  <sbeamer@eecs.berkeley.edu>
 2017-08-16 18:00:58 -04:00